Commit cd89483a authored by Richard Acayan's avatar Richard Acayan Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sdm670: add gpu 



The Snapdragon 670 has the Adreno A615 GPU. Add it along with its device
tree dependencies.

Signed-off-by: default avatarRichard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240806214452.16406-10-mailingradian@gmail.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 0f432547

arch/arm64/boot/dts/qcom/sdm670.dtsi

+180 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include <dt-bindings/clock/qcom,dispcc-sdm845.h>

#include <dt-bindings/clock/qcom,gcc-sdm845.h>

#include <dt-bindings/clock/qcom,gpucc-sdm845.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/dma/qcom-gpi.h>

#include <dt-bindings/gpio/gpio.h>
@@ -617,6 +618,11 @@ qfprom: qfprom@784000 { 
			#address-cells = <1>;

			#size-cells = <1>;



			gpu_speed_bin: gpu_speed_bin@1a2 {

				reg = <0x1a2 0x2>;

				bits = <5 8>;

			};



			qusb2_hstx_trim: hstx-trim@1eb {

				reg = <0x1eb 0x1>;

				bits = <1 4>;
@@ -1299,6 +1305,180 @@ rclk-pins { 
			};

		};



		gpu: gpu@5000000 {

			compatible = "qcom,adreno-615.0", "qcom,adreno";



			reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>;

			reg-names = "kgsl_3d0_reg_memory", "cx_mem";



			/*

			 * Look ma, no clocks! The GPU clocks and power are

			 * controlled entirely by the GMU

			 */



			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;



			iommus = <&adreno_smmu 0>;



			operating-points-v2 = <&gpu_opp_table>;



			qcom,gmu = <&gmu>;



			interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>;

			interconnect-names = "gfx-mem";



			nvmem-cells = <&gpu_speed_bin>;

			nvmem-cell-names = "speed_bin";



			status = "disabled";



			gpu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-780000000 {

					opp-hz = /bits/ 64 <780000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0x8>;

				};



				opp-750000000 {

					opp-hz = /bits/ 64 <750000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0x8>;

				};



				opp-700000000 {

					opp-hz = /bits/ 64 <700000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0x4>;

				};



				opp-650000000 {

					opp-hz = /bits/ 64 <650000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0xc>;

				};



				opp-565000000 {

					opp-hz = /bits/ 64 <565000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0xc>;

				};



				opp-504000000 {

					opp-hz = /bits/ 64 <504000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0x2>;

				};



				opp-430000000 {

					opp-hz = /bits/ 64 <430000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

					opp-peak-kBps = <7216000>;

					opp-supported-hw = <0xf>;

				};



				opp-355000000 {

					opp-hz = /bits/ 64 <355000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;

					opp-peak-kBps = <6220000>;

					opp-supported-hw = <0xf>;

				};



				opp-267000000 {

					opp-hz = /bits/ 64 <267000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

					opp-peak-kBps = <4068000>;

					opp-supported-hw = <0xf>;

				};



				opp-180000000 {

					opp-hz = /bits/ 64 <180000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

					opp-peak-kBps = <1804000>;

					opp-supported-hw = <0xf>;

				};

			};

		};



		adreno_smmu: iommu@5040000 {

			compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";

			reg = <0 0x05040000 0 0x10000>;

			#iommu-cells = <1>;

			#global-interrupts = <2>;

			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;

			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,

				 <&gcc GCC_GPU_CFG_AHB_CLK>;

			clock-names = "bus", "iface";



			power-domains = <&gpucc GPU_CX_GDSC>;

		};



		gmu: gmu@506a000 {

			compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";



			reg = <0 0x0506a000 0 0x30000>,

			      <0 0x0b280000 0 0x10000>,

			      <0 0x0b480000 0 0x10000>;

			reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";



			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "hfi", "gmu";



			clocks = <&gpucc GPU_CC_CX_GMU_CLK>,

				 <&gpucc GPU_CC_CXO_CLK>,

				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,

				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;

			clock-names = "gmu", "cxo", "axi", "memnoc";



			power-domains = <&gpucc GPU_CX_GDSC>,

					<&gpucc GPU_GX_GDSC>;

			power-domain-names = "cx", "gx";



			iommus = <&adreno_smmu 5>;



			operating-points-v2 = <&gmu_opp_table>;



			gmu_opp_table: opp-table {

				compatible = "operating-points-v2";



				opp-200000000 {

					opp-hz = /bits/ 64 <200000000>;

					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;

				};

			};

		};



		gpucc: clock-controller@5090000 {

			compatible = "qcom,sdm845-gpucc";

			reg = <0 0x05090000 0 0x9000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			clock-names = "bi_tcxo",

				      "gcc_gpu_gpll0_clk_src",

				      "gcc_gpu_gpll0_div_clk_src";

		};



		usb_1_hsphy: phy@88e2000 {

			compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";

			reg = <0 0x088e2000 0 0x400>;