Commit ce025130 authored by Timur Kristóf's avatar Timur Kristóf Committed by Alex Deucher
Browse files

drm/amd/pm: Adjust si_upload_smc_data register programming (v3) 



Based on some comments in dm_pp_display_configuration
above the crtc_index and line_time fields, these values
are programmed to the SMC to work around an SMC hang
when it switches MCLK.

According to Alex, the Windows driver programs them to:
mclk_change_block_cp_min = 200 / line_time
mclk_change_block_cp_max = 100 / line_time
Let's use the same for the sake of consistency.

Previously we used the watermark values, but it seemed buggy
as the code was mixing up low/high and A/B watermarks, and
was not saving a low watermark value on DCE 6, so
mclk_change_block_cp_max would be always zero previously.

Split this change off from the previous si_upload_smc_data
to make it easier to bisect, in case it causes any issues.

Fixes: 841686df ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarTimur Kristóf <timur.kristof@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a43b2cec

drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c

+2 −2
Original line number Diff line number Diff line
@@ -5833,8 +5833,8 @@ static int si_upload_smc_data(struct amdgpu_device *adev) 
		crtc_index = amdgpu_crtc->crtc_id;



		if (amdgpu_crtc->line_time) {

			mclk_change_block_cp_min = amdgpu_crtc->wm_high / amdgpu_crtc->line_time;

			mclk_change_block_cp_max = amdgpu_crtc->wm_low / amdgpu_crtc->line_time;

			mclk_change_block_cp_min = 200 / amdgpu_crtc->line_time;

			mclk_change_block_cp_max = 100 / amdgpu_crtc->line_time;

		}

	}