Commit ce0c43e8 authored by Richard Zhu's avatar Richard Zhu Committed by Manivannan Sadhasivam
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PCI: imx6: Add workaround for errata ERR051624 



ERR051624: The Controller Without Vaux Cannot Exit L23 Ready Through Beacon
or PERST# De-assertion

When the auxiliary power is not available, the controller cannot exit from
L23 Ready with beacon or PERST# de-assertion when main power is not
removed. So the workaround is to set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.

This workaround is required irrespective of whether Vaux is supplied to the
link partner or not.

Signed-off-by: default avatarRichard Zhu <hongxing.zhu@nxp.com>
[mani: subject and description rewording]
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarFrank Li <Frank.Li@nxp.com>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://patch.msgid.link/20250416081314.3929794-5-hongxing.zhu@nxp.com
parent 47f54a90

drivers/pci/controller/dwc/pci-imx6.c

+15 −0
Original line number Diff line number Diff line
@@ -48,6 +48,8 @@ 
#define IMX95_PCIE_SS_RW_REG_0			0xf0

#define IMX95_PCIE_REF_CLKEN			BIT(23)

#define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)

#define IMX95_PCIE_SS_RW_REG_1			0xf4

#define IMX95_PCIE_SYS_AUX_PWR_DET		BIT(31)



#define IMX95_PE0_GEN_CTRL_1			0x1050

#define IMX95_PCIE_DEVICE_TYPE			GENMASK(3, 0)
@@ -227,6 +229,19 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) 


static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)

{

	/*

	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready

	 * Through Beacon or PERST# De-assertion

	 *

	 * When the auxiliary power is not available, the controller

	 * cannot exit from L23 Ready with beacon or PERST# de-assertion

	 * when main power is not removed.

	 *

	 * Workaround: Set SS_RW_REG_1[SYS_AUX_PWR_DET] to 1.

	 */

	regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1,

			IMX95_PCIE_SYS_AUX_PWR_DET);



	regmap_update_bits(imx_pcie->iomuxc_gpr,

			IMX95_PCIE_SS_RW_REG_0,

			IMX95_PCIE_PHY_CR_PARA_SEL,