Commit ce29261e authored by Sascha Bischoff's avatar Sascha Bischoff Committed by Marc Zyngier
Browse files

KVM: arm64: selftests: Add no-vgic-v5 selftest 



Now that GICv5 is supported, it is important to check that all of the
GICv5 register state is hidden from a guest that doesn't create a
vGICv5.

Rename the no-vgic-v3 selftest to no-vgic, and extend it to check
GICv5 system registers too.

Signed-off-by: default avatarSascha Bischoff <sascha.bischoff@arm.com>
Link: https://patch.msgid.link/20260319154937.3619520-42-sascha.bischoff@arm.com


Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 0a9f38bf

tools/testing/selftests/kvm/Makefile.kvm

+1 −1
Original line number Diff line number Diff line
@@ -179,7 +179,7 @@ TEST_GEN_PROGS_arm64 += arm64/vgic_irq 
TEST_GEN_PROGS_arm64 += arm64/vgic_lpi_stress

TEST_GEN_PROGS_arm64 += arm64/vgic_v5

TEST_GEN_PROGS_arm64 += arm64/vpmu_counter_access

TEST_GEN_PROGS_arm64 += arm64/no-vgic-v3

TEST_GEN_PROGS_arm64 += arm64/no-vgic

TEST_GEN_PROGS_arm64 += arm64/idreg-idst

TEST_GEN_PROGS_arm64 += arm64/kvm-uuid

TEST_GEN_PROGS_arm64 += access_tracking_perf_test

tools/testing/selftests/kvm/arm64/no-vgic-v3.c→tools/testing/selftests/kvm/arm64/no-vgic.c

+297 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



// Check that, on a GICv3 system, not configuring GICv3 correctly

// results in all of the sysregs generating an UNDEF exception.

// Check that, on a GICv3-capable system (GICv3 native, or GICv5 with

// FEAT_GCIE_LEGACY), not configuring GICv3 correctly results in all

// of the sysregs generating an UNDEF exception. Do the same for GICv5

// on a GICv5 host.



#include <test_util.h>

#include <kvm_util.h>

#include <processor.h>



#include <arm64/gic_v5.h>



static volatile bool handled;



#define __check_sr_read(r)					\
@@ -27,6 +31,24 @@ static volatile bool handled; 
		isb();						\

	} while (0)



#define __check_gicv5_gicr_op(r)				\

	({							\

		uint64_t val;					\

								\

		handled = false;				\

		dsb(sy);					\

		val = read_sysreg_s(GICV5_OP_GICR_ ## r);	\

		val;						\

	})



#define __check_gicv5_gic_op(r)					\

	do {							\

		handled = false;				\

		dsb(sy);					\

		write_sysreg_s(0, GICV5_OP_GIC_ ## r);		\

		isb();						\

	} while (0)



/* Fatal checks */

#define check_sr_read(r)					\

	do {							\
@@ -46,7 +68,19 @@ static volatile bool handled; 
		check_sr_write(r);		\

	} while (0)



static void guest_code(void)

#define check_gicv5_gicr_op(r)					\

	do {							\

		__check_gicv5_gicr_op(r);			\

		__GUEST_ASSERT(handled, #r " no read trap");	\

	} while (0)



#define check_gicv5_gic_op(r)					\

	do {							\

		__check_gicv5_gic_op(r);			\

		__GUEST_ASSERT(handled, #r " no write trap");	\

	} while (0)



static void guest_code_gicv3(void)

{

	uint64_t val;
@@ -61,7 +95,7 @@ static void guest_code(void) 
	/*

	 * Access all GICv3 registers, and fail if we don't get an UNDEF.

	 * Note that we happily access all the APxRn registers without

	 * checking their existance, as all we want to see is a failure.

	 * checking their existence, as all we want to see is a failure.

	 */

	check_sr_rw(ICC_PMR_EL1);

	check_sr_read(ICC_IAR0_EL1);
@@ -109,6 +143,72 @@ static void guest_code(void) 
	GUEST_DONE();

}



static void guest_code_gicv5(void)

{

	/*

	 * Check that we advertise that ID_AA64PFR2_EL1.GCIE == 0, having

	 * hidden the feature at runtime without any other userspace action.

	 */

	__GUEST_ASSERT(FIELD_GET(ID_AA64PFR2_EL1_GCIE,

				 read_sysreg_s(SYS_ID_AA64PFR2_EL1)) == 0,

		       "GICv5 wrongly advertised");



	/*

	 * Try all GICv5 instructions, and fail if we don't get an UNDEF.

	 */

	check_gicv5_gic_op(CDAFF);

	check_gicv5_gic_op(CDDI);

	check_gicv5_gic_op(CDDIS);

	check_gicv5_gic_op(CDEOI);

	check_gicv5_gic_op(CDHM);

	check_gicv5_gic_op(CDPEND);

	check_gicv5_gic_op(CDPRI);

	check_gicv5_gic_op(CDRCFG);

	check_gicv5_gicr_op(CDIA);

	check_gicv5_gicr_op(CDNMIA);



	/* Check General System Register acccesses */

	check_sr_rw(ICC_APR_EL1);

	check_sr_rw(ICC_CR0_EL1);

	check_sr_read(ICC_HPPIR_EL1);

	check_sr_read(ICC_IAFFIDR_EL1);

	check_sr_rw(ICC_ICSR_EL1);

	check_sr_read(ICC_IDR0_EL1);

	check_sr_rw(ICC_PCR_EL1);



	/* Check PPI System Register accessess */

	check_sr_rw(ICC_PPI_CACTIVER0_EL1);

	check_sr_rw(ICC_PPI_CACTIVER1_EL1);

	check_sr_rw(ICC_PPI_SACTIVER0_EL1);

	check_sr_rw(ICC_PPI_SACTIVER1_EL1);

	check_sr_rw(ICC_PPI_CPENDR0_EL1);

	check_sr_rw(ICC_PPI_CPENDR1_EL1);

	check_sr_rw(ICC_PPI_SPENDR0_EL1);

	check_sr_rw(ICC_PPI_SPENDR1_EL1);

	check_sr_rw(ICC_PPI_ENABLER0_EL1);

	check_sr_rw(ICC_PPI_ENABLER1_EL1);

	check_sr_read(ICC_PPI_HMR0_EL1);

	check_sr_read(ICC_PPI_HMR1_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR0_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR1_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR2_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR3_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR4_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR5_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR6_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR7_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR8_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR9_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR10_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR11_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR12_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR13_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR14_EL1);

	check_sr_rw(ICC_PPI_PRIORITYR15_EL1);



	GUEST_DONE();

}



static void guest_undef_handler(struct ex_regs *regs)

{

	/* Success, we've gracefully exploded! */
@@ -138,12 +238,12 @@ static void test_run_vcpu(struct kvm_vcpu *vcpu) 
	} while (uc.cmd != UCALL_DONE);

}



static void test_guest_no_gicv3(void)

static void test_guest_no_vgic(void *guest_code)

{

	struct kvm_vcpu *vcpu;

	struct kvm_vm *vm;



	/* Create a VM without a GICv3 */

	/* Create a VM without a GIC */

	vm = vm_create_with_one_vcpu(&vcpu, guest_code);



	vm_init_descriptor_tables(vm);
@@ -161,17 +261,37 @@ int main(int argc, char *argv[]) 
{

	struct kvm_vcpu *vcpu;

	struct kvm_vm *vm;

	uint64_t pfr0;

	bool has_v3, has_v5;

	uint64_t pfr;



	test_disable_default_vgic();



	vm = vm_create_with_one_vcpu(&vcpu, NULL);

	pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));

	__TEST_REQUIRE(FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr0),

		       "GICv3 not supported.");



	pfr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));

	has_v3 = !!FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr);



	pfr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR2_EL1));

	has_v5 = !!FIELD_GET(ID_AA64PFR2_EL1_GCIE, pfr);



	kvm_vm_free(vm);



	test_guest_no_gicv3();

	__TEST_REQUIRE(has_v3 || has_v5,

		       "Neither GICv3 nor GICv5 supported.");



	if (has_v3) {

		pr_info("Testing no-vgic-v3\n");

		test_guest_no_vgic(guest_code_gicv3);

	} else {

		pr_info("No GICv3 support: skipping no-vgic-v3 test\n");

	}



	if (has_v5) {

		pr_info("Testing no-vgic-v5\n");

		test_guest_no_vgic(guest_code_gicv5);

	} else {

		pr_info("No GICv5 support: skipping no-vgic-v5 test\n");

	}



	return 0;

}