Commit ce3d5af2 authored by Kotaro, Tokai's avatar Kotaro, Tokai Committed by Namhyung Kim
Browse files

perf vendor events arm64: Update FUJITSU-MONAKA pmu event 

Update pmu events for FUJITSU-MONAKA.
And, also updated common-and-microarch.json.

FUJITSU-MONAKA PMU Events Specification v1.1 and Errata v1.0 URL:
https://github.com/fujitsu/FUJITSU-MONAKA

Arm Architecture Reference Version L.b URL:
https://developer.arm.com/documentation/ddi0487/lb/?lang=en



Signed-off-by: default avatarKotaro, Tokai <fj0635gf@aa.jp.fujitsu.com>
Reviewed-by: default avatarJames Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20250618063618.1244363-1-fj0635gf@aa.jp.fujitsu.com


Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent ae075693

tools/perf/pmu-events/arch/arm64/common-and-microarch.json

+70 −0
Original line number Diff line number Diff line
@@ -1833,5 +1833,75 @@ 
        "EventCode": "0x8324",

        "EventName": "L1I_CACHE_REFILL_PERCYC",

        "BriefDescription": "Level 1 instruction or unified cache refills in progress."

    },

    {

        "EventCode": "0x8431",

        "EventName": "ASE_FP_VREDUCE_SPEC",

        "BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise or reduction."

    },

    {

        "EventCode": "0x8432",

        "EventName": "SVE_FP_PREDUCE_SPEC",

        "BriefDescription": "Floating-point operation_speculatively_executed, Advanced SIMD pairwise add step or pairwise reduce step."

    },

    {

        "EventCode": "0x8443",

        "EventName": "ASE_FP_BF16_MIN_SPEC",

        "BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x8444",

        "EventName": "ASE_FP_FP8_MIN_SPEC",

        "BriefDescription": "Advanced SIMD data processing operation speculatively_executed, smallest type is 8-bit floating-point."

    },

    {

        "EventCode": "0x844B",

        "EventName": "ASE_SVE_FP_BF16_MIN_SPEC",

        "BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x844C",

        "EventName": "ASE_SVE_FP_FP8_MIN_SPEC",

        "BriefDescription": "Advanced SIMD data processing or SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."

    },

    {

        "EventCode": "0x8463",

        "EventName": "SVE_FP_BF16_MIN_SPEC",

        "BriefDescription": "SVE data processing operation speculatively_executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x8464",

        "EventName": "SVE_FP_FP8_MIN_SPEC",

        "BriefDescription": "SVE data processing operation speculatively_executed, smallest type is 8-bit floating-point."

    },

    {

        "EventCode": "0x8473",

        "EventName": "FP_BF16_MIN_SPEC",

        "BriefDescription": "Floating-point operation speculatively_executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x8474",

        "EventName": "FP_FP8_MIN_SPEC",

        "BriefDescription": "Floating-point operation speculatively_executed, smallest type is 8-bit floating-point."

    },

    {

        "EventCode": "0x8483",

        "EventName": "FP_BF16_FIXED_MIN_OPS_SPEC",

        "BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x8484",

        "EventName": "FP_FP8_FIXED_MIN_OPS_SPEC",

        "BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."

    },

    {

        "EventCode": "0x848B",

        "EventName": "FP_BF16_SCALE_MIN_OPS_SPEC",

        "BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is BFloat16 floating-point."

    },

    {

        "EventCode": "0x848C",

        "EventName": "FP_FP8_SCALE_MIN_OPS_SPEC",

        "BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."

    }

]

tools/perf/pmu-events/arch/arm64/fujitsu/monaka/core-imp-def.json

+1 −1
Original line number Diff line number Diff line 
[

    {

        "ArchStdEvent": "L1I_CACHE_PRF",

        "BriefDescription": "This event counts fetch counted by either Level 1 instruction hardware prefetch or Level 1 instruction software prefetch."

        "BriefDescription": "This event counts L1I_CACHE caused by hardware prefetch or software prefetch."

    }

]

tools/perf/pmu-events/arch/arm64/fujitsu/monaka/cycle_accounting.json

+2 −2
Original line number Diff line number Diff line
@@ -12,12 +12,12 @@ 
    {

        "EventCode": "0x0184",

        "EventName": "LD_COMP_WAIT",

        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache and memory access."

        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted load/store/prefetch operation waits for L1D cache, L2 cache, L3 cache and memory access."

    },

    {

        "EventCode": "0x0185",

        "EventName": "LD_COMP_WAIT_EX",

        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache and memory access."

        "BriefDescription": "This event counts every cycle that no instruction was committed because the oldest and uncommitted integer load operation waits for L1D cache, L2 cache, L3 cache and memory access."

    },

    {

        "EventCode": "0x0186",

tools/perf/pmu-events/arch/arm64/fujitsu/monaka/exception.json

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
    },

    {

        "ArchStdEvent": "EXC_SMC",

        "BriefDescription": "This event counts only Secure Monitor Call exceptions. The counter does not increment on SMC instructions trapped as a Hyp Trap exception."

        "BriefDescription": "This event counts only Secure Monitor Call exceptions. This event does not increment on SMC instructions trapped as a Hyp Trap exception."

    },

    {

        "ArchStdEvent": "EXC_HVC",

tools/perf/pmu-events/arch/arm64/fujitsu/monaka/fp_operation.json

+77 −21
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
    {

        "EventCode": "0x0105",

        "EventName": "FP_MV_SPEC",

        "BriefDescription": "This event counts architecturally executed floating-point move operations."

        "BriefDescription": "This event counts architecturally executed floating-point move operation."

    },

    {

        "EventCode": "0x0112",
@@ -24,7 +24,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point operation."

    },

    {

        "ArchStdEvent": "FP_HP_SPEC",
@@ -40,7 +40,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_HP_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE half-precision floating-point operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE half-precision floating-point operation."

    },

    {

        "ArchStdEvent": "FP_SP_SPEC",
@@ -56,7 +56,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_SP_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE single-precision floating-point operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE single-precision floating-point operation."

    },

    {

        "ArchStdEvent": "FP_DP_SPEC",
@@ -72,7 +72,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_DP_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE double-precision floating-point operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE double-precision floating-point operation."

    },

    {

        "ArchStdEvent": "FP_DIV_SPEC",
@@ -88,7 +88,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_DIV_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point divide operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point divide operation."

    },

    {

        "ArchStdEvent": "FP_SQRT_SPEC",
@@ -104,7 +104,7 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_SQRT_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point square root operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point square root operation."

    },

    {

        "ArchStdEvent": "ASE_FP_FMA_SPEC",
@@ -116,11 +116,11 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_FMA_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point FMA operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point FMA operation."

    },

    {

        "ArchStdEvent": "FP_MUL_SPEC",

        "BriefDescription": "This event counts architecturally executed floating-point multiply operations."

        "BriefDescription": "This event counts architecturally executed floating-point multiply operation."

    },

    {

        "ArchStdEvent": "ASE_FP_MUL_SPEC",
@@ -132,11 +132,11 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_MUL_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point multiply operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point multiply operation."

    },

    {

        "ArchStdEvent": "FP_ADDSUB_SPEC",

        "BriefDescription": "This event counts architecturally executed floating-point add or subtract operations."

        "BriefDescription": "This event counts architecturally executed floating-point add or subtract operation."

    },

    {

        "ArchStdEvent": "ASE_FP_ADDSUB_SPEC",
@@ -148,19 +148,19 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_ADDSUB_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point add or subtract operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point add or subtract operation."

    },

    {

        "ArchStdEvent": "ASE_FP_RECPE_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point reciprocal estimate operation."

    },

    {

        "ArchStdEvent": "SVE_FP_RECPE_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operations."

        "BriefDescription": "This event counts architecturally executed SVE floating-point reciprocal estimate operation."

    },

    {

        "ArchStdEvent": "ASE_SVE_FP_RECPE_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point reciprocal estimate operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point reciprocal estimate operation."

    },

    {

        "ArchStdEvent": "ASE_FP_CVT_SPEC",
@@ -172,15 +172,15 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_CVT_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point convert operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point convert operation."

    },

    {

        "ArchStdEvent": "SVE_FP_AREDUCE_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operations."

        "BriefDescription": "This event counts architecturally executed SVE floating-point accumulating reduction operation."

    },

    {

        "ArchStdEvent": "ASE_FP_PREDUCE_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point pairwise add step operation."

    },

    {

        "ArchStdEvent": "SVE_FP_VREDUCE_SPEC",
@@ -188,15 +188,15 @@ 
    },

    {

        "ArchStdEvent": "ASE_SVE_FP_VREDUCE_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD and SVE floating-point vector reduction operations."

        "BriefDescription": "This event counts architecturally executed Advanced SIMD or SVE floating-point vector reduction operation."

    },

    {

        "ArchStdEvent": "FP_SCALE_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE arithmetic operations. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."

        "BriefDescription": "This event counts architecturally executed SVE arithmetic operation. See FP_SCALE_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by (128 / CSIZE) and by twice that amount for operations that would also be counted by SVE_FP_FMA_SPEC."

    },

    {

        "ArchStdEvent": "FP_FIXED_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operations. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. The event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."

        "BriefDescription": "This event counts architecturally executed v8SIMD&FP arithmetic operation. See FP_FIXED_OPS_SPEC of ARMv9 Reference Manual for more information. This event counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations, and by twice those amounts for operations that would also be counted by FP_FMA_SPEC."

    },

    {

        "ArchStdEvent": "ASE_SVE_FP_DOT_SPEC",
@@ -205,5 +205,61 @@ 
    {

        "ArchStdEvent": "ASE_SVE_FP_MMLA_SPEC",

        "BriefDescription": "This event counts architecturally executed microarchitectural Advanced SIMD or SVE floating-point matrix multiply operation."

    },

    {

        "ArchStdEvent": "ASE_FP_VREDUCE_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD floating-point vector reduction operation."

    },

    {

        "ArchStdEvent": "SVE_FP_PREDUCE_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE floating-point pairwise add step operation."

    },

    {

        "ArchStdEvent": "ASE_FP_BF16_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "ASE_FP_FP8_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD data processing operations, smallest type is 8-bit floating-point."

    },

    {

        "ArchStdEvent": "ASE_SVE_FP_BF16_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "ASE_SVE_FP_FP8_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed Advanced SIMD data processing or SVE data processing operations, smallest type is 8-bit floating-point."

    },

    {

        "ArchStdEvent": "SVE_FP_BF16_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "SVE_FP_FP8_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed SVE data processing operations, smallest type is 8-bit floating-point."

    },

    {

        "ArchStdEvent": "FP_BF16_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed data processing operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "FP_FP8_MIN_SPEC",

        "BriefDescription": "This event counts architecturally executed data processing operations, smallest type is 8-bit floating-point."

    },

    {

        "ArchStdEvent": "FP_BF16_FIXED_MIN_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "FP_FP8_FIXED_MIN_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed non-scalable element arithmetic operations, smallest type is 8-bit floating-point."

    },

    {

        "ArchStdEvent": "FP_BF16_SCALE_MIN_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is BFloat16 floating-point."

    },

    {

        "ArchStdEvent": "FP_FP8_SCALE_MIN_OPS_SPEC",

        "BriefDescription": "This event counts architecturally executed scalable element arithmetic operations, smallest type is 8-bit floating-point."

    }

]