Commit ce649bd2 authored by Leo Ma's avatar Leo Ma Committed by Alex Deucher
Browse files

drm/amd/display: Fix DC mode screen flickering on DCN321 



[Why && How]
Screen flickering saw on 4K@60 eDP with high refresh rate external
monitor when booting up in DC mode. DC Mode Capping is disabled
which caused wrong UCLK being used.

Reviewed-by: default avatarAlvin Lee <alvin.lee2@amd.com>
Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarLeo Ma <hanghong.ma@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0e62103b

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+12 −3
Original line number Diff line number Diff line
@@ -712,6 +712,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
					 * since we calculate mode support based on softmax being the max UCLK

					 * frequency.

					 */

					if (dc->debug.disable_dc_mode_overwrite) {

						dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);

					} else

						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,

								dc->clk_mgr->bw_params->dc_mode_softmax_memclk);

				} else {
@@ -746,8 +750,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base, 
		/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */

		if (clk_mgr_base->clks.p_state_change_support &&

				(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support) &&

				!dc->work_arounds.clock_update_disable_mask.uclk)

				!dc->work_arounds.clock_update_disable_mask.uclk) {

			if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)

				dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,

						max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));



			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));

		}



		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&

				clk_mgr_base->clks.num_ways > new_clocks->num_ways) {