Commit cea573a8 authored Dec 03, 2025 by LinCheng Ku Committed by Alex Deucher Dec 16, 2025

drm/amd/display: Add USB-C DP Alt Mode lane limitation in DCN32



[Why]
USB-C DisplayPort Alt Mode with concurrent USB data needs lane count
limitation to prevent incorrect 4-lane DP configuration when only 2 lanes
are available due to hardware lane sharing between DP and USB3.

[How]
Query DMUB for Alt Mode status (is_dp_alt_disable, is_usb, is_dp4) in
dcn32_link_encoder_get_max_link_cap() and cap DP to 2 lanes when USB is
active on USB-C port. Added inline documentation explaining the USB-C
lane sharing constraint.

Reviewed-by: PeiChen Huang <peichen.huang@amd.com>
Signed-off-by: LinCheng Ku <lincheng.ku@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent db2373ad

drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c

+12 −3

Original line number	Diff line number	Diff line
		@@ -188,9 +188,18 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc,
		if (!query_dp_alt_from_dmub(enc, &cmd))
		return;

		if (cmd.query_dp_alt.data.is_usb &&
		cmd.query_dp_alt.data.is_dp4 == 0)
		link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
		/*
		* USB-C DisplayPort Alt Mode lane count limitation logic:
		* When USB and DP share the same USB-C connector, hardware must allocate
		* some lanes for USB data, limiting DP to maximum 2 lanes instead of 4.
		* This ensures USB functionality remains available while DP is active.
		*/
		if (cmd.query_dp_alt.data.is_dp_alt_disable == 0 &&
		cmd.query_dp_alt.data.is_usb &&
		cmd.query_dp_alt.data.is_dp4 == 0) {
		link_settings->lane_count =
		MIN(LANE_COUNT_TWO, link_settings->lane_count);
		}
		}