Commit ceb9314f authored by Michael Ellerman's avatar Michael Ellerman Committed by Andrew Morton
Browse files

powerpc/64e: drop E500 ifdefs in 64-bit code 

All 64-bit Book3E have E500=y, so drop the unneeded ifdefs.

Link: https://lkml.kernel.org/r/7fb88809c88a1b774063eda602a9333079403f83.1719928057.git.christophe.leroy@csgroup.eu


Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Cc: Jason Gunthorpe <jgg@nvidia.com>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Oscar Salvador <osalvador@suse.de>
Cc: Peter Xu <peterx@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
parent a898530e

arch/powerpc/mm/nohash/tlb_64e.c

+0 −12
Original line number Diff line number Diff line
@@ -85,7 +85,6 @@ static void __init setup_page_sizes(void) 
	unsigned int eptcfg;

	int psize;



#ifdef CONFIG_PPC_E500

	unsigned int mmucfg = mfspr(SPRN_MMUCFG);

	int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
@@ -151,7 +150,6 @@ static void __init setup_page_sizes(void) 


		goto out;

	}

#endif

out:

	/* Cleanup array and print summary */

	pr_info("MMU: Supported page sizes\n");
@@ -180,13 +178,11 @@ static void __init setup_mmu_htw(void) 
	 */



	switch (book3e_htw_mode) {

#ifdef CONFIG_PPC_E500

	case PPC_HTW_E6500:

		extlb_level_exc = EX_TLB_SIZE;

		patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);

		patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);

		break;

#endif

	}

	pr_info("MMU: Book3E HW tablewalk %s\n",

		book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
@@ -217,7 +213,6 @@ static void early_init_this_mmu(void) 
	}

	mtspr(SPRN_MAS4, mas4);



#ifdef CONFIG_PPC_E500

	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

		unsigned int num_cams;

		bool map = true;
@@ -238,7 +233,6 @@ static void early_init_this_mmu(void) 
			linear_map_top = map_mem_in_cams(linear_map_top,

							 num_cams, false, true);

	}

#endif



	/* A sync won't hurt us after mucking around with

	 * the MMU configuration
@@ -270,7 +264,6 @@ static void __init early_init_mmu_global(void) 
	/* Look for HW tablewalk support */

	setup_mmu_htw();



#ifdef CONFIG_PPC_E500

	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

		if (book3e_htw_mode == PPC_HTW_NONE) {

			extlb_level_exc = EX_TLB_SIZE;
@@ -279,7 +272,6 @@ static void __init early_init_mmu_global(void) 
				exc_instruction_tlb_miss_bolted_book3e);

		}

	}

#endif



	/* Set the global containing the top of the linear mapping

	 * for use by the TLB miss code
@@ -291,7 +283,6 @@ static void __init early_init_mmu_global(void) 


static void __init early_mmu_set_memory_limit(void)

{

#ifdef CONFIG_PPC_E500

	if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

		/*

		 * Limit memory so we dont have linear faults.
@@ -302,7 +293,6 @@ static void __init early_mmu_set_memory_limit(void) 
		 */

		memblock_enforce_memory_limit(linear_map_top);

	}

#endif



	memblock_set_current_limit(linear_map_top);

}
@@ -340,7 +330,6 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base, 
	 * We crop it to the size of the first MEMBLOCK to

	 * avoid going over total available memory just in case...

	 */

#ifdef CONFIG_PPC_E500

	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {

		unsigned long linear_sz;

		unsigned int num_cams;
@@ -353,7 +342,6 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base, 


		ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);

	} else

#endif

		ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);



	/* Finally limit subsequent allocations */