Commit ced65deb authored by Jiadong Zhu's avatar Jiadong Zhu Committed by Alex Deucher
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drm/amdgpu/mes11: update mes_reset_queue function to support sdma queue 



Reset sdma queue through mmio based on me_id and queue_id.

v2: simplify callflows and register calculation.

Signed-off-by: default avatarJiadong Zhu <Jiadong.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d7d2688b

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+1 −1
Original line number Diff line number Diff line
@@ -905,7 +905,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 
	queue_input.me_id = ring->me;

	queue_input.pipe_id = ring->pipe;

	queue_input.queue_id = ring->queue;

	queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);

	queue_input.mqd_addr = ring->mqd_obj ? amdgpu_bo_gpu_offset(ring->mqd_obj) : 0;

	queue_input.wptr_addr = ring->wptr_gpu_addr;

	queue_input.vmid = vmid;

	queue_input.use_mmio = use_mmio;

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+26 −1
Original line number Diff line number Diff line
@@ -366,7 +366,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ 
				      uint32_t queue_id, uint32_t vmid)

{

	struct amdgpu_device *adev = mes->adev;

	uint32_t value;

	uint32_t value, reg;

	int i, r = 0;



	amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
@@ -424,6 +424,31 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ 
		}

		soc21_grbm_select(adev, 0, 0, 0, 0);

		mutex_unlock(&adev->srbm_mutex);

	} else if (queue_type == AMDGPU_RING_TYPE_SDMA) {

		dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n",

			 me_id, pipe_id, queue_id);

		switch (me_id) {

		case 1:

			reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ);

			break;

		case 0:

		default:

			reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ);

			break;

		}



		value = 1 << queue_id;

		WREG32(reg, value);

		/* wait for queue reset done */

		for (i = 0; i < adev->usec_timeout; i++) {

			if (!(RREG32(reg) & value))

				break;

			udelay(1);

		}

		if (i >= adev->usec_timeout) {

			dev_err(adev->dev, "failed to wait on sdma queue reset done\n");

			r = -ETIMEDOUT;

		}

	}



	amdgpu_gfx_rlc_exit_safe_mode(adev, 0);