Commit ced86959 authored by Shyam Sundar S K's avatar Shyam Sundar S K Committed by Alexandre Belloni
Browse files

i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold 



The current driver sets the response buffer threshold value to 1
(N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD
I3C controller only generates interrupts when the response buffer
threshold value is set to 0 (1 DWORD).

Therefore, a quirk is added to set the response buffer threshold value
to 0.

Reviewed-by: default avatarJarkko Nikula <jarkko.nikula@linux.intel.com>
Co-developed-by: default avatarKrishnamoorthi M <krishnamoorthi.m@amd.com>
Signed-off-by: default avatarKrishnamoorthi M <krishnamoorthi.m@amd.com>
Co-developed-by: default avatarGuruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: default avatarGuruvendra Punugupati <Guruvendra.Punugupati@amd.com>
Signed-off-by: default avatarShyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20240829091713.736217-7-Shyam-sundar.S-k@amd.com


Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent 46d4daa5

drivers/i3c/master/mipi-i3c-hci/core.c

+5 −1
Original line number Diff line number Diff line
@@ -146,6 +146,10 @@ static int i3c_hci_bus_init(struct i3c_master_controller *m) 
	if (ret)

		return ret;



	/* Set RESP_BUF_THLD to 0(n) to get 1(n+1) response */

	if (hci->quirks & HCI_QUIRK_RESP_BUF_THLD)

		amd_set_resp_buf_thld(hci);



	reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);

	DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL));
@@ -842,7 +846,7 @@ static const __maybe_unused struct of_device_id i3c_hci_of_match[] = { 
MODULE_DEVICE_TABLE(of, i3c_hci_of_match);



static const struct acpi_device_id i3c_hci_acpi_match[] = {

	{ "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING },

	{ "AMDI5017", HCI_QUIRK_PIO_MODE | HCI_QUIRK_OD_PP_TIMING | HCI_QUIRK_RESP_BUF_THLD },

	{}

};

MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match);

drivers/i3c/master/mipi-i3c-hci/hci.h

+2 −0
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ struct i3c_hci_dev_data { 
#define HCI_QUIRK_RAW_CCC	BIT(1)	/* CCC framing must be explicit */

#define HCI_QUIRK_PIO_MODE	BIT(2)  /* Set PIO mode for AMD platforms */

#define HCI_QUIRK_OD_PP_TIMING		BIT(3)  /* Set OD and PP timings for AMD platforms */

#define HCI_QUIRK_RESP_BUF_THLD		BIT(4)  /* Set resp buf thld to 0 for AMD platforms */





/* global functions */
@@ -149,5 +150,6 @@ void mipi_i3c_hci_resume(struct i3c_hci *hci); 
void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);

void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);

void amd_set_od_pp_timing(struct i3c_hci *hci);

void amd_set_resp_buf_thld(struct i3c_hci *hci);



#endif

drivers/i3c/master/mipi-i3c-hci/hci_quirks.c

+11 −0
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 
#define AMD_SCL_I3C_OD_TIMING          0x00cf00cf

#define AMD_SCL_I3C_PP_TIMING          0x00160016



#define QUEUE_THLD_CTRL                0xD0



void amd_set_od_pp_timing(struct i3c_hci *hci)

{

	u32 data;
@@ -31,3 +33,12 @@ void amd_set_od_pp_timing(struct i3c_hci *hci) 
	data |= W0_MASK(18, 16);

	reg_write(HCI_SDA_HOLD_SWITCH_DLY_TIMING, data);

}



void amd_set_resp_buf_thld(struct i3c_hci *hci)

{

	u32 data;



	data = reg_read(QUEUE_THLD_CTRL);

	data = data & ~W0_MASK(15, 8);

	reg_write(QUEUE_THLD_CTRL, data);

}