Commit ceeb0da0 authored by Ira Weiny's avatar Ira Weiny Committed by Dan Williams
Browse files

cxl/mem: Adjust ram/pmem range to represent DPA ranges 



CXL spec defines the volatile DPA range to be 0 to Volatile memory size.
It further defines the persistent DPA range to follow directly after the
end of the Volatile DPA through the persistent memory size.  Essentially

Volatile DPA range   = [0, Volatile size)
Persistent DPA range = [Volatile size, Volatile size + Persistent size)

Adjust the pmem_range start to reflect this and remote the TODO.

Signed-off-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20210617221620.1904031-4-ira.weiny@intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent f847502a

drivers/cxl/pci.c

+6 −8
Original line number Diff line number Diff line
@@ -1441,8 +1441,9 @@ static int cxl_mem_create_range_info(struct cxl_mem *cxlm) 
	if (cxlm->partition_align_bytes == 0) {

		cxlm->ram_range.start = 0;

		cxlm->ram_range.end = cxlm->volatile_only_bytes - 1;

		cxlm->pmem_range.start = 0;

		cxlm->pmem_range.end = cxlm->persistent_only_bytes - 1;

		cxlm->pmem_range.start = cxlm->volatile_only_bytes;

		cxlm->pmem_range.end = cxlm->volatile_only_bytes +

					cxlm->persistent_only_bytes - 1;

		return 0;

	}
@@ -1466,15 +1467,12 @@ static int cxl_mem_create_range_info(struct cxl_mem *cxlm) 
			cxlm->next_volatile_bytes,

			cxlm->next_persistent_bytes);



	/*

	 * TODO: enumerate DPA map, as 'ram' and 'pmem' do not alias.

	 * For now, only the capacity is exported in sysfs

	 */

	cxlm->ram_range.start = 0;

	cxlm->ram_range.end = cxlm->active_volatile_bytes - 1;



	cxlm->pmem_range.start = 0;

	cxlm->pmem_range.end = cxlm->active_persistent_bytes - 1;

	cxlm->pmem_range.start = cxlm->active_volatile_bytes;

	cxlm->pmem_range.end = cxlm->active_volatile_bytes +

				cxlm->active_persistent_bytes - 1;



	return 0;

}