Commit cef4f1b5 authored by Parthiban Nallathambi's avatar Parthiban Nallathambi Committed by Linus Walleij
Browse files

pinctrl: sunxi: add missed lvds pins for a100/a133 



lvds, lcd, dsi all shares the same GPIO D bank and lvds0
data 3 lines and lvds1 pins are missed, add them.

Signed-off-by: default avatarParthiban Nallathambi <parthiban@linumiz.com>
Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 0e18b099

drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c

+12 −0
Original line number Diff line number Diff line
@@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = { 
		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */

		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D3P */

		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DP3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */

		  SUNXI_FUNCTION(0x3, "lvds0"),		/* D3N */

		  SUNXI_FUNCTION(0x4, "dsi0"),		/* DM3 */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D0P */

		  SUNXI_FUNCTION(0x4, "spi1"),		/* CS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D0N */

		  SUNXI_FUNCTION(0x4, "spi1"),		/* CLK */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D1P */

		  SUNXI_FUNCTION(0x4, "spi1"),		/* MOSI */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D1N */

		  SUNXI_FUNCTION(0x4, "spi1"),		/* MISO */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D2P */

		  SUNXI_FUNCTION(0x4, "uart3"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D2N */

		  SUNXI_FUNCTION(0x4, "uart3"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* CKP */

		  SUNXI_FUNCTION(0x4, "uart3"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* CKN */

		  SUNXI_FUNCTION(0x4, "uart3"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D3P */

		  SUNXI_FUNCTION(0x4, "uart4"),		/* TX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */

		  SUNXI_FUNCTION(0x3, "lvds1"),		/* D3N */

		  SUNXI_FUNCTION(0x4, "uart4"),		/* RX */

		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),

	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),