Commit cef73007 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Helgaas
Browse files

PCI: dwc: Support 16-lane operation 



Some hosts support 16 lanes of PCIe. Make num-lanes accept that number.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20250926-topic-pcie_16ln-v1-1-c249acc18790@oss.qualcomm.com
parent 8f5ae30d

drivers/pci/controller/dwc/pcie-designware.c

+3 −0
Original line number Diff line number Diff line
@@ -841,6 +841,9 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) 
	case 8:

		plc |= PORT_LINK_MODE_8_LANES;

		break;

	case 16:

		plc |= PORT_LINK_MODE_16_LANES;

		break;

	default:

		dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);

		return;

drivers/pci/controller/dwc/pcie-designware.h

+1 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ 
#define PORT_LINK_MODE_2_LANES		PORT_LINK_MODE(0x3)

#define PORT_LINK_MODE_4_LANES		PORT_LINK_MODE(0x7)

#define PORT_LINK_MODE_8_LANES		PORT_LINK_MODE(0xf)

#define PORT_LINK_MODE_16_LANES		PORT_LINK_MODE(0x1f)



#define PCIE_PORT_LANE_SKEW		0x714

#define PORT_LANE_SKEW_INSERT_MASK	GENMASK(23, 0)