Commit cf05922d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2025-03-12' of... 

Merge tag 'drm-intel-gt-next-2025-03-12' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

UAPI Changes:

- Increase I915_PARAM_MMAP_GTT_VERSION version to indicate support for partial mmaps (José Roberto de Souza)

Driver Changes:

Fixes/improvements/new stuff:

- Implement vmap/vunmap GEM object functions (Asbjørn Sloth Tønnesen)

Miscellaneous:

- Various register definition cleanups (Ville Syrjälä)
- Fix typo in a comment [gt/uc] (Yuichiro Tsuji)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Z9IXs5CzHHKScuQn@linux
parents a82866fb bfef148f

drivers/gpu/drm/i915/gem/i915_gem_mman.c

+4 −1
Original line number Diff line number Diff line
@@ -164,6 +164,9 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj) 
 * 4 - Support multiple fault handlers per object depending on object's

 *     backing storage (a.k.a. MMAP_OFFSET).

 *

 * 5 - Support multiple partial mmaps(mmap part of BO + unmap a offset, multiple

 *     times with different size and offset).

 *

 * Restrictions:

 *

 *  * snoopable objects cannot be accessed via the GTT. It can cause machine
@@ -191,7 +194,7 @@ static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj) 
 */

int i915_gem_mmap_gtt_version(void)

{

	return 4;

	return 5;

}



static inline struct i915_gtt_view

drivers/gpu/drm/i915/gem/i915_gem_object.c

+26 −0
Original line number Diff line number Diff line
@@ -873,6 +873,30 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) 
	return lmem_placement;

}



static int i915_gem_vmap_object(struct drm_gem_object *gem_obj,

				struct iosys_map *map)

{

	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);

	void *vaddr;



	vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);

	if (IS_ERR(vaddr))

		return PTR_ERR(vaddr);



	iosys_map_set_vaddr(map, vaddr);



	return 0;

}



static void i915_gem_vunmap_object(struct drm_gem_object *gem_obj,

				   struct iosys_map *map)

{

	struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);



	i915_gem_object_flush_map(obj);

	i915_gem_object_unpin_map(obj);

}



void i915_gem_init__objects(struct drm_i915_private *i915)

{

	INIT_WORK(&i915->mm.free_work, __i915_gem_free_work);
@@ -896,6 +920,8 @@ static const struct drm_gem_object_funcs i915_gem_object_funcs = { 
	.free = i915_gem_free_object,

	.close = i915_gem_close_object,

	.export = i915_gem_prime_export,

	.vmap = i915_gem_vmap_object,

	.vunmap = i915_gem_vunmap_object,

};



/**

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+2 −3
Original line number Diff line number Diff line
@@ -769,9 +769,8 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) 
	if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))

		media_fuse = ~media_fuse;



	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

		      GEN11_GT_VEBOX_DISABLE_SHIFT;

	vdbox_mask = REG_FIELD_GET(GEN11_GT_VDBOX_DISABLE_MASK, media_fuse);

	vebox_mask = REG_FIELD_GET(GEN11_GT_VEBOX_DISABLE_MASK, media_fuse);



	if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {

		fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);

drivers/gpu/drm/i915/gt/intel_gt.c

+38 −51
Original line number Diff line number Diff line
@@ -302,44 +302,32 @@ static void gen6_check_faults(struct intel_gt *gt) 
{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	unsigned long fault;



	for_each_engine(engine, gt, id) {

		u32 fault;



		fault = GEN6_RING_FAULT_REG_READ(engine);



		if (fault & RING_FAULT_VALID) {

			gt_dbg(gt, "Unexpected fault\n"

			       "\tAddr: 0x%08lx\n"

			       "\tAddr: 0x%08x\n"

			       "\tAddress space: %s\n"

			       "\tSource ID: %ld\n"

			       "\tType: %ld\n",

			       fault & PAGE_MASK,

			       "\tSource ID: %d\n"

			       "\tType: %d\n",

			       fault & RING_FAULT_VADDR_MASK,

			       fault & RING_FAULT_GTTSEL_MASK ?

			       "GGTT" : "PPGTT",

			       RING_FAULT_SRCID(fault),

			       RING_FAULT_FAULT_TYPE(fault));

			       REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

			       REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

		}

	}

}



static void xehp_check_faults(struct intel_gt *gt)

static void gen8_report_fault(struct intel_gt *gt, u32 fault,

			      u32 fault_data0, u32 fault_data1)

{

	u32 fault;



	/*

	 * Although the fault register now lives in an MCR register range,

	 * the GAM registers are special and we only truly need to read

	 * the "primary" GAM instance rather than handling each instance

	 * individually.  intel_gt_mcr_read_any() will automatically steer

	 * toward the primary instance.

	 */

	fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);

	if (fault & RING_FAULT_VALID) {

		u32 fault_data0, fault_data1;

	u64 fault_addr;



		fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);

		fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);



	fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

		((u64)fault_data0 << 12);
@@ -351,10 +339,27 @@ static void xehp_check_faults(struct intel_gt *gt) 
	       "\tType: %d\n",

	       upper_32_bits(fault_addr), lower_32_bits(fault_addr),

	       fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

		       GEN8_RING_FAULT_ENGINE_ID(fault),

		       RING_FAULT_SRCID(fault),

		       RING_FAULT_FAULT_TYPE(fault));

	       REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),

	       REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

	       REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

}



static void xehp_check_faults(struct intel_gt *gt)

{

	u32 fault;



	/*

	 * Although the fault register now lives in an MCR register range,

	 * the GAM registers are special and we only truly need to read

	 * the "primary" GAM instance rather than handling each instance

	 * individually.  intel_gt_mcr_read_any() will automatically steer

	 * toward the primary instance.

	 */

	fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);

	if (fault & RING_FAULT_VALID)

		gen8_report_fault(gt, fault,

				  intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0),

				  intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1));

}



static void gen8_check_faults(struct intel_gt *gt)
@@ -374,28 +379,10 @@ static void gen8_check_faults(struct intel_gt *gt) 
	}



	fault = intel_uncore_read(uncore, fault_reg);

	if (fault & RING_FAULT_VALID) {

		u32 fault_data0, fault_data1;

		u64 fault_addr;



		fault_data0 = intel_uncore_read(uncore, fault_data0_reg);

		fault_data1 = intel_uncore_read(uncore, fault_data1_reg);



		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

			     ((u64)fault_data0 << 12);



		gt_dbg(gt, "Unexpected fault\n"

		       "\tAddr: 0x%08x_%08x\n"

		       "\tAddress space: %s\n"

		       "\tEngine ID: %d\n"

		       "\tSource ID: %d\n"

		       "\tType: %d\n",

		       upper_32_bits(fault_addr), lower_32_bits(fault_addr),

		       fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

		       GEN8_RING_FAULT_ENGINE_ID(fault),

		       RING_FAULT_SRCID(fault),

		       RING_FAULT_FAULT_TYPE(fault));

	}

	if (fault & RING_FAULT_VALID)

		gen8_report_fault(gt, fault,

				  intel_uncore_read(uncore, fault_data0_reg),

				  intel_uncore_read(uncore, fault_data1_reg));

}



void intel_gt_check_and_clear_faults(struct intel_gt *gt)

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

+3 −7
Original line number Diff line number Diff line
@@ -35,9 +35,7 @@ static u32 gen11_get_crystal_clock_freq(struct intel_uncore *uncore, 
	u32 f24_mhz = 24000000;

	u32 f25_mhz = 25000000;

	u32 f38_4_mhz = 38400000;

	u32 crystal_clock =

		(rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>

		GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;

	u32 crystal_clock = rpm_config_reg & GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK;



	switch (crystal_clock) {

	case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
@@ -80,8 +78,7 @@ static u32 gen11_read_clock_frequency(struct intel_uncore *uncore) 
		 * register increments from this frequency (it might

		 * increment only every few clock cycle).

		 */

		freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>

			      GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);

		freq >>= 3 - REG_FIELD_GET(GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, c0);

	}



	return freq;
@@ -102,8 +99,7 @@ static u32 gen9_read_clock_frequency(struct intel_uncore *uncore) 
		 * register increments from this frequency (it might

		 * increment only every few clock cycle).

		 */

		freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>

			      CTC_SHIFT_PARAMETER_SHIFT);

		freq >>= 3 - REG_FIELD_GET(CTC_SHIFT_PARAMETER_MASK, ctc_reg);

	}



	return freq;