Commit cf79814c authored by Fudongwang's avatar Fudongwang Committed by Alex Deucher
Browse files

drm/amd/display: fix disable otg wa logic in DCN316 



[Why]
Wrong logic cause screen corruption.

[How]
Port logic from DCN35/314.

Cc: stable@vger.kernel.org
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarFudongwang <fudong.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 95392758

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+12 −7
Original line number Diff line number Diff line
@@ -99,20 +99,25 @@ static int dcn316_get_active_display_cnt_wa( 
	return display_count;

}



static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)

static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,

		bool safe_to_lower, bool disable)

{

	struct dc *dc = clk_mgr_base->ctx->dc;

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; ++i) {

		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];

		struct pipe_ctx *pipe = safe_to_lower

			? &context->res_ctx.pipe_ctx[i]

			: &dc->current_state->res_ctx.pipe_ctx[i];



		if (pipe->top_pipe || pipe->prev_odm_pipe)

			continue;

		if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||

				     dc_is_virtual_signal(pipe->stream->signal))) {

		if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||

				     !pipe->stream->link_enc)) {

			if (disable) {

				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)

					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);



				reset_sync_context_for_pipe(dc, context, i);

			} else

				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
@@ -207,11 +212,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, 
	}



	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {

		dcn316_disable_otg_wa(clk_mgr_base, context, true);

		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);



		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;

		dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);

		dcn316_disable_otg_wa(clk_mgr_base, context, false);

		dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);



		update_dispclk = true;

	}