Commit cf87f46f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-05-11' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "This should be the last set of fixes for 6.9, i915, xe and amdgpu are
  the bulk here, one of the previous nouveau fixes turned up an issue,
  so reverting it, otherwise one core and a couple of meson fixes.

  core:
   - fix connector debugging output

  i915:
   - Automate CCS Mode setting during engine resets
   - Fix audio time stamp programming for DP
   - Fix parsing backlight BDB data

  xe:
   - Fix use zero-length element array
   - Move more from system wq to ordered private wq
   - Do not ignore return for drmm_mutex_init

  amdgpu:
   - DCN 3.5 fix
   - MST DSC fixes
   - S0i3 fix
   - S4 fix
   - HDP MMIO mapping fix
   - Fix a regression in visible vram handling

  amdkfd:
   - Spatial partition fix

  meson:
   - dw-hdmi: power-up fixes
   - dw-hdmi: add badngap setting for g12

  nouveau:
   - revert SG_DEBUG fix that has a side effect"

* tag 'drm-fixes-2024-05-11' of https://gitlab.freedesktop.org/drm/kernel:
  Revert "drm/nouveau/firmware: Fix SG_DEBUG error with nvkm_firmware_ctor()"
  drm/amdgpu: Fix comparison in amdgpu_res_cpu_visible
  drm/amdkfd: don't allow mapping the MMIO HDP page with large pages
  drm/xe: Use ordered WQ for G2H handler
  drm/xe/guc: Check error code when initializing the CT mutex
  drm/xe/ads: Use flexible-array
  Revert "drm/amdkfd: Add partition id field to location_id"
  dm/amd/pm: Fix problems with reboot/shutdown for some SMU 13.0.4/13.0.11 users
  drm/amd/display: MST DSC check for older devices
  drm/amd/display: Fix idle optimization checks for multi-display and dual eDP
  drm/amd/display: Fix DSC-re-computing
  drm/amd/display: Enable urgent latency adjustments for DCN35
  drm/connector: Add \n to message about demoting connector force-probes
  drm/i915/bios: Fix parsing backlight BDB data
  drm/i915/audio: Fix audio time stamp programming for DP
  drm/i915/gt: Automate CCS Mode setting during engine resets
  drm/meson: dw-hdmi: add bandgap setting for g12
  drm/meson: dw-hdmi: power up phy on device init
parents c22c3e07 a222a647

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+1 −1
Original line number Diff line number Diff line
@@ -427,7 +427,7 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev, 


	amdgpu_res_first(res, 0, res->size, &cursor);

	while (cursor.remaining) {

		if ((cursor.start + cursor.size) >= adev->gmc.visible_vram_size)

		if ((cursor.start + cursor.size) > adev->gmc.visible_vram_size)

			return false;

		amdgpu_res_next(&cursor, cursor.size);

	}

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+5 −2
Original line number Diff line number Diff line
@@ -1139,7 +1139,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, 
			goto err_unlock;

		}

		offset = dev->adev->rmmio_remap.bus_addr;

		if (!offset) {

		if (!offset || (PAGE_SIZE > 4096)) {

			err = -ENOMEM;

			goto err_unlock;

		}
@@ -2307,7 +2307,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, 
			return -EINVAL;

		}

		offset = pdd->dev->adev->rmmio_remap.bus_addr;

		if (!offset) {

		if (!offset || (PAGE_SIZE > 4096)) {

			pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");

			return -ENOMEM;

		}
@@ -3349,6 +3349,9 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, 
	if (vma->vm_end - vma->vm_start != PAGE_SIZE)

		return -EINVAL;



	if (PAGE_SIZE > 4096)

		return -EINVAL;



	address = dev->adev->rmmio_remap.bus_addr;



	vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |

drivers/gpu/drm/amd/amdkfd/kfd_topology.c

+2 −3
Original line number Diff line number Diff line
@@ -1997,9 +1997,8 @@ int kfd_topology_add_device(struct kfd_node *gpu) 
			HSA_CAP_ASIC_REVISION_MASK);



	dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);

	/* On multi-partition nodes, node id = location_id[31:28] */

	if (gpu->kfd->num_nodes > 1)

		dev->node_props.location_id |= (dev->gpu->node_id << 28);

	if (KFD_GC_VERSION(dev->gpu->kfd) == IP_VERSION(9, 4, 3))

		dev->node_props.location_id |= dev->gpu->node_id;



	dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);

	dev->node_props.max_engine_clk_fcompute =

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+13 −3
Original line number Diff line number Diff line
@@ -1219,8 +1219,10 @@ static bool is_dsc_need_re_compute( 
	if (dc_link->type != dc_connection_mst_branch)

		return false;



	if (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||

		dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))

	/* add a check for older MST DSC with no virtual DPCDs */

	if (needs_dsc_aux_workaround(dc_link)  &&

		(!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||

		dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT)))

		return false;



	for (i = 0; i < MAX_PIPES; i++)
@@ -1240,7 +1242,15 @@ static bool is_dsc_need_re_compute( 
			continue;



		aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context;

		if (!aconnector)

		if (!aconnector || !aconnector->dsc_aux)

			continue;



		/*

		 *	check if cached virtual MST DSC caps are available and DSC is supported

		 *	as per specifications in their Virtual DPCD registers.

		*/

		if (!(aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported ||

			aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))

			continue;



		stream_on_link[new_stream_on_link_num] = aconnector;

drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c

+2 −2
Original line number Diff line number Diff line
@@ -195,9 +195,9 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { 
	.dcn_downspread_percent = 0.5,

	.gpuvm_min_page_size_bytes = 4096,

	.hostvm_min_page_size_bytes = 4096,

	.do_urgent_latency_adjustment = 0,

	.do_urgent_latency_adjustment = 1,

	.urgent_latency_adjustment_fabric_clock_component_us = 0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 0,

	.urgent_latency_adjustment_fabric_clock_reference_mhz = 3000,

};



void dcn35_build_wm_range_table_fpu(struct clk_mgr *clk_mgr)