Commit cfa0904a authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Prevent Gating DTBCLK before It Is Properly Latched 

[why]
1. With allow_0_dtb_clk enabled, the time required to latch DTBCLK to 600 MHz
depends on the SMU. If DTBCLK is not latched to 600 MHz before set_mode completes,
gating DTBCLK causes the DP2 sink to lose its clock source.

2. The existing DTBCLK gating sequence ungates DTBCLK based on both pix_clk and ref_dtbclk,
but gates DTBCLK when either pix_clk or ref_dtbclk is zero.
pix_clk can be zero outside the set_mode sequence before DTBCLK is properly latched,
which can lead to DTBCLK being gated by mistake.

[how]
Consider both pixel_clk and ref_dtbclk when determining when it is safe to gate DTBCLK;
this is more accurate.

Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4701


Fixes: 5949e7c4 ("drm/amd/display: Enable Dynamic DTBCLK Switch")
Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit d04eb0c4)
Cc: stable@vger.kernel.org
parent 6a23ae0a

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

+3 −1
Original line number Diff line number Diff line
@@ -394,6 +394,8 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, 
	display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);

	if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)

		new_clocks->ref_dtbclk_khz = 600000;

	else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000)

		new_clocks->ref_dtbclk_khz = 0;



	/*

	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
@@ -435,7 +437,7 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, 


			actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);



			if (actual_dtbclk) {

			if (actual_dtbclk > 590000) {

				clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;

				clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;

			}

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

+1 −1
Original line number Diff line number Diff line
@@ -1411,7 +1411,7 @@ static void dccg35_set_dtbclk_dto( 
				__func__, params->otg_inst, params->pixclk_khz,

				params->ref_dtbclk_khz, req_dtbclk_khz, phase, modulo);



	} else {

	} else if (!params->ref_dtbclk_khz && !req_dtbclk_khz) {

		switch (params->otg_inst) {

		case 0:

			REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);