Commit cfd4951f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.11-2021-02-03' of... 

Merge tag 'amd-drm-fixes-5.11-2021-02-03' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.11-2021-02-03:

amdgpu:
- Fix retry in gem create
- Vangogh fixes
- Fix for display from shared buffers
- Various display fixes

amdkfd:
- Fix regression in buffer free

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210204041300.4425-1-alexander.deucher@amd.com
parents 6fc5e302 8e92bb0f

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+6 −10
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include <linux/sched/task.h>



#include "amdgpu_object.h"

#include "amdgpu_gem.h"

#include "amdgpu_vm.h"

#include "amdgpu_amdkfd.h"

#include "amdgpu_dma_buf.h"
@@ -1152,7 +1153,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 
	struct sg_table *sg = NULL;

	uint64_t user_addr = 0;

	struct amdgpu_bo *bo;

	struct amdgpu_bo_param bp;

	struct drm_gem_object *gobj;

	u32 domain, alloc_domain;

	u64 alloc_flags;

	int ret;
@@ -1220,19 +1221,14 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 
	pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n",

			va, size, domain_string(alloc_domain));



	memset(&bp, 0, sizeof(bp));

	bp.size = size;

	bp.byte_align = 1;

	bp.domain = alloc_domain;

	bp.flags = alloc_flags;

	bp.type = bo_type;

	bp.resv = NULL;

	ret = amdgpu_bo_create(adev, &bp, &bo);

	ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags,

				       bo_type, NULL, &gobj);

	if (ret) {

		pr_debug("Failed to create BO on domain %s. ret %d\n",

			 domain_string(alloc_domain), ret);

		goto err_bo_create;

	}

	bo = gem_to_amdgpu_bo(gobj);

	if (bo_type == ttm_bo_type_sg) {

		bo->tbo.sg = sg;

		bo->tbo.ttm->sg = sg;

drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

+6 −2
Original line number Diff line number Diff line
@@ -926,8 +926,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, 
				       struct drm_file *file_priv,

				       const struct drm_mode_fb_cmd2 *mode_cmd)

{

	struct drm_gem_object *obj;

	struct amdgpu_framebuffer *amdgpu_fb;

	struct drm_gem_object *obj;

	struct amdgpu_bo *bo;

	uint32_t domains;

	int ret;



	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);
@@ -938,7 +940,9 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, 
	}



	/* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */

	if (obj->import_attach) {

	bo = gem_to_amdgpu_bo(obj);

	domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags);

	if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) {

		drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n");

		return ERR_PTR(-EINVAL);

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+1 −1
Original line number Diff line number Diff line
@@ -269,8 +269,8 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 
		resv = vm->root.base.bo->tbo.base.resv;

	}



retry:

	initial_domain = (u32)(0xffffffff & args->in.domains);

retry:

	r = amdgpu_gem_object_create(adev, size, args->in.alignment,

				     initial_domain,

				     flags, ttm_bo_type_device, resv, &gobj);

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+1 −1
Original line number Diff line number Diff line
@@ -897,7 +897,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
		return -EINVAL;



	/* A shared bo cannot be migrated to VRAM */

	if (bo->prime_shared_count) {

	if (bo->prime_shared_count || bo->tbo.base.import_attach) {

		if (domain & AMDGPU_GEM_DOMAIN_GTT)

			domain = AMDGPU_GEM_DOMAIN_GTT;

		else

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −2
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ 
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580

#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0



#define mmCGTS_TCC_DISABLE_Vangogh                0x5006

#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX       1

#define mmCGTS_USER_TCC_DISABLE_Vangogh                0x5007

#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
@@ -4936,8 +4940,18 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 
static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)

{

	/* TCCs are global (not instanced). */

	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

	uint32_t tcc_disable;



	switch (adev->asic_type) {

	case CHIP_VANGOGH:

		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |

				RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);

		break;

	default:

		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

				RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);

		break;

	}



	adev->gfx.config.tcc_disabled_mask =

		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |