Commit d045f4ad authored by lima1002's avatar lima1002 Committed by Alex Deucher
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drm/amd/swsmu: Update smu v14.0.0 headers to be 14.0.1 compatible 



update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarlima1002 <li.ma@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8966c316

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

+32 −1
Original line number Diff line number Diff line
@@ -144,6 +144,37 @@ typedef struct { 
  uint32_t MaxGfxClk;

} DpmClocks_t;



//Freq in MHz

//Voltage in milli volts with 2 fractional bits

typedef struct {

  uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];

  uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];

  uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];

  uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];

  uint32_t VClocks0[NUM_VCN_DPM_LEVELS];

  uint32_t VClocks1[NUM_VCN_DPM_LEVELS];

  uint32_t DClocks0[NUM_VCN_DPM_LEVELS];

  uint32_t DClocks1[NUM_VCN_DPM_LEVELS];

  uint32_t VPEClocks[NUM_VPE_DPM_LEVELS];

  uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS];

  uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS];

  uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];

  MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS];



  uint8_t  NumDcfClkLevelsEnabled;

  uint8_t  NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk

  uint8_t  NumSocClkLevelsEnabled;

  uint8_t  Vcn0ClkLevelsEnabled;     //Applies to both Vclk0 and Dclk0

  uint8_t  Vcn1ClkLevelsEnabled;     //Applies to both Vclk1 and Dclk1

  uint8_t  VpeClkLevelsEnabled;

  uint8_t  NumMemPstatesEnabled;

  uint8_t  NumFclkLevelsEnabled;

  uint8_t  spare;



  uint32_t MinGfxClk;

  uint32_t MaxGfxClk;

} DpmClocks_t_v14_0_1;



typedef struct {

  uint16_t CoreFrequency[16];          //Target core frequency [MHz]

  uint16_t CorePower[16];              //CAC calculated core power [mW]
@@ -224,7 +255,7 @@ typedef enum { 
#define TABLE_CUSTOM_DPM            2 // Called by Driver

#define TABLE_BIOS_GPIO_CONFIG      3 // Called by BIOS

#define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS

#define TABLE_SPARE0                5 // Unused

#define TABLE_MOMENTARY_PM          5 // Called by Tools

#define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log

#define TABLE_SMU_METRICS           7 // Called by Driver and SMF/PMF

#define TABLE_COUNT                 8

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

+46 −9
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ 
#define FEATURE_EDC_BIT                      7

#define FEATURE_PLL_POWER_DOWN_BIT           8

#define FEATURE_VDDOFF_BIT                   9

#define FEATURE_VCN_DPM_BIT                 10

#define FEATURE_VCN_DPM_BIT                 10   /* this is for both VCN0 and VCN1 */

#define FEATURE_DS_MPM_BIT                  11

#define FEATURE_FCLK_DPM_BIT                12

#define FEATURE_SOCCLK_DPM_BIT              13
@@ -56,9 +56,9 @@ 
#define FEATURE_DS_GFXCLK_BIT               21

#define FEATURE_DS_SOCCLK_BIT               22

#define FEATURE_DS_LCLK_BIT                 23

#define FEATURE_LOW_POWER_DCNCLKS_BIT       24  // for all DISP clks

#define FEATURE_LOW_POWER_DCNCLKS_BIT       24

#define FEATURE_DS_SHUBCLK_BIT              25

#define FEATURE_SPARE0_BIT                  26  //SPARE

#define FEATURE_RESERVED0_BIT               26

#define FEATURE_ZSTATES_BIT                 27

#define FEATURE_IOMMUL2_PG_BIT              28

#define FEATURE_DS_FCLK_BIT                 29
@@ -66,8 +66,8 @@ 
#define FEATURE_DS_MP1CLK_BIT               31

#define FEATURE_WHISPER_MODE_BIT            32

#define FEATURE_SMU_LOW_POWER_BIT           33

#define FEATURE_SMART_L3_RINSER_BIT         34

#define FEATURE_SPARE1_BIT                  35  //SPARE

#define FEATURE_RESERVED1_BIT               34  /* v14_0_0 SMART_L3_RINSER; v14_0_1 RESERVED1 */

#define FEATURE_GFX_DEM_BIT                 35  /* v14_0_0 SPARE; v14_0_1 GFX_DEM */

#define FEATURE_PSI_BIT                     36

#define FEATURE_PROCHOT_BIT                 37

#define FEATURE_CPUOFF_BIT                  38
@@ -77,11 +77,11 @@ 
#define FEATURE_PERF_LIMIT_BIT              42

#define FEATURE_CORE_DLDO_BIT               43

#define FEATURE_DVO_BIT                     44

#define FEATURE_DS_VCN_BIT                  45

#define FEATURE_DS_VCN_BIT                  45  /* v14_0_1 this is for both VCN0 and VCN1 */

#define FEATURE_CPPC_BIT                    46

#define FEATURE_CPPC_PREFERRED_CORES        47

#define FEATURE_DF_CSTATES_BIT              48

#define FEATURE_SPARE2_BIT                  49  //SPARE

#define FEATURE_FAST_PSTATE_CLDO_BIT        49  /* v14_0_0 SPARE */

#define FEATURE_ATHUB_PG_BIT                50

#define FEATURE_VDDOFF_ECO_BIT              51

#define FEATURE_ZSTATES_ECO_BIT             52
@@ -93,8 +93,8 @@ 
#define FEATURE_DS_IPUCLK_BIT               58

#define FEATURE_DS_VPECLK_BIT               59

#define FEATURE_VPE_DPM_BIT                 60

#define FEATURE_SPARE_61                    61

#define FEATURE_FP_DIDT                     62

#define FEATURE_SMART_L3_RINSER_BIT         61  /* v14_0_0 SPARE*/

#define FEATURE_PCC_BIT                     62  /* v14_0_0 FP_DIDT v14_0_1 PCC_BIT */

#define NUM_FEATURES                        63



// Firmware Header/Footer
@@ -151,6 +151,43 @@ typedef struct { 
  // MP1_EXT_SCRATCH7 = RTOS Current Job

} FwStatus_t;



typedef struct {

  // MP1_EXT_SCRATCH0

  uint32_t DpmHandlerID         : 8;

  uint32_t ActivityMonitorID    : 8;

  uint32_t DpmTimerID           : 8;

  uint32_t DpmHubID             : 4;

  uint32_t DpmHubTask           : 4;

  // MP1_EXT_SCRATCH1

  uint32_t CclkSyncStatus       : 8;

  uint32_t ZstateStatus         : 4;

  uint32_t Cpu1VddOff           : 4;

  uint32_t DstateFun            : 4;

  uint32_t DstateDev            : 4;

  uint32_t GfxOffStatus         : 2;

  uint32_t Cpu0Off              : 2;

  uint32_t Cpu1Off              : 2;

  uint32_t Cpu0VddOff           : 2;

  // MP1_EXT_SCRATCH2

  uint32_t P2JobHandler         :32;

  // MP1_EXT_SCRATCH3

  uint32_t PostCode             :32;

  // MP1_EXT_SCRATCH4

  uint32_t MsgPortBusy          :15;

  uint32_t RsmuPmiP1Pending     : 1;

  uint32_t RsmuPmiP2PendingCnt  : 8;

  uint32_t DfCstateExitPending  : 1;

  uint32_t Pc6EntryPending      : 1;

  uint32_t Pc6ExitPending       : 1;

  uint32_t WarmResetPending     : 1;

  uint32_t Mp0ClkPending        : 1;

  uint32_t InWhisperMode        : 1;

  uint32_t spare2               : 2;

  // MP1_EXT_SCRATCH5

  uint32_t IdleMask             :32;

  // MP1_EXT_SCRATCH6 = RTOS threads' status

  // MP1_EXT_SCRATCH7 = RTOS Current Job

} FwStatus_t_v14_0_1;



#pragma pack(pop)

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h

+8 −10
Original line number Diff line number Diff line
@@ -72,23 +72,19 @@ 
#define PPSMC_MSG_SetHardMinSocclkByFreq        0x13 ///< Set hard min for SOC CLK

#define PPSMC_MSG_SetSoftMinFclk                0x14 ///< Set hard min for FCLK

#define PPSMC_MSG_SetSoftMinVcn0                0x15 ///< Set soft min for VCN0 clocks (VCLK0 and DCLK0)



#define PPSMC_MSG_EnableGfxImu                  0x16 ///< Enable GFX IMU



#define PPSMC_MSG_spare_0x17                    0x17

#define PPSMC_MSG_spare_0x18                    0x18

#define PPSMC_MSG_spare_0x17                    0x17 ///< Get GFX clock frequency

#define PPSMC_MSG_spare_0x18                    0x18 ///< Get FCLK frequency

#define PPSMC_MSG_AllowGfxOff                   0x19 ///< Inform PMFW of allowing GFXOFF entry

#define PPSMC_MSG_DisallowGfxOff                0x1A ///< Inform PMFW of disallowing GFXOFF entry

#define PPSMC_MSG_SetSoftMaxGfxClk              0x1B ///< Set soft max for GFX CLK

#define PPSMC_MSG_SetHardMinGfxClk              0x1C ///< Set hard min for GFX CLK



#define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK

#define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK

#define PPSMC_MSG_SetSoftMaxVcn0                0x1F ///< Set soft max for VCN0 clocks (VCLK0 and DCLK0)

#define PPSMC_MSG_spare_0x20                    0x20

#define PPSMC_MSG_spare_0x20                    0x20 ///< Set power limit percentage

#define PPSMC_MSG_PowerDownJpeg0                0x21 ///< Power down Jpeg of VCN0

#define PPSMC_MSG_PowerUpJpeg0                  0x22 ///< Power up Jpeg of VCN0; VCN0 is power gated by default



#define PPSMC_MSG_SetHardMinFclkByFreq          0x23 ///< Set hard min for FCLK

#define PPSMC_MSG_SetSoftMinSocclkByFreq        0x24 ///< Set soft min for SOC CLK

#define PPSMC_MSG_AllowZstates                  0x25 ///< Inform PMFM of allowing Zstate entry, i.e. no Miracast activity
@@ -99,8 +95,8 @@ 
#define PPSMC_MSG_PowerUpIspByTile              0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM

#define PPSMC_MSG_SetHardMinIspiclkByFreq       0x2B ///< Set HardMin by frequency for ISPICLK

#define PPSMC_MSG_SetHardMinIspxclkByFreq       0x2C ///< Set HardMin by frequency for ISPXCLK

#define PPSMC_MSG_PowerDownUmsch                0x2D ///< Power down VCN.UMSCH (aka VSCH) scheduler

#define PPSMC_MSG_PowerUpUmsch                  0x2E ///< Power up VCN.UMSCH (aka VSCH) scheduler

#define PPSMC_MSG_PowerDownUmsch                0x2D ///< Power down VCN0.UMSCH (aka VSCH) scheduler

#define PPSMC_MSG_PowerUpUmsch                  0x2E ///< Power up VCN0.UMSCH (aka VSCH) scheduler

#define PPSMC_Message_IspStutterOn_MmhubPgDis   0x2F ///< ISP StutterOn mmHub PgDis

#define PPSMC_Message_IspStutterOff_MmhubPgEn   0x30 ///< ISP StufferOff mmHub PgEn

#define PPSMC_MSG_PowerUpVpe                    0x31 ///< Power up VPE
@@ -110,7 +106,9 @@ 
#define PPSMC_MSG_DisableLSdma                  0x35 ///< Disable LSDMA

#define PPSMC_MSG_SetSoftMaxVpe                 0x36 ///<

#define PPSMC_MSG_SetSoftMinVpe                 0x37 ///<

#define PPSMC_Message_Count                     0x38 ///< Total number of PPSMC messages

#define PPSMC_MSG_AllocMALLCache                0x38 ///< Allocating MALL Cache

#define PPSMC_MSG_ReleaseMALLCache              0x39 ///< Releasing MALL Cache

#define PPSMC_Message_Count                     0x3A ///< Total number of PPSMC messages

/** @}*/



/**

drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h

+1 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 


#define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF

#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7

#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6

#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1



#define FEATURE_MASK(feature) (1ULL << feature)

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c

+1 −1
Original line number Diff line number Diff line
@@ -234,7 +234,7 @@ int smu_v14_0_check_fw_version(struct smu_context *smu) 
		smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;

		break;

	case IP_VERSION(14, 0, 1):

		smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_0;

		smu->smc_driver_if_version = SMU14_DRIVER_IF_VERSION_SMU_V14_0_1;

		break;



	default: