Commit d0e164f7 authored by Cruise Hung's avatar Cruise Hung Committed by Alex Deucher
Browse files

drm/amd/display: Remove check DPIA HPD status for BW Allocation 



[Why & How]
Link hpd_status is for embedded DPIA only.
Do not check hpd_status for BW allocation logic.

Reviewed-by: default avatarMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: default avatarCruise Hung <Cruise.Hung@amd.com>
Signed-off-by: default avatarIvan Lipski <ivan.lipski@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 04112dce

drivers/gpu/drm/amd/display/dc/link/link_validation.c

+4 −2
Original line number Diff line number Diff line
@@ -408,8 +408,10 @@ enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const stru 
		link = stream->link;



		if (!(link && (stream->signal == SIGNAL_TYPE_DISPLAY_PORT

				|| stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

				&& link->hpd_status))

				|| stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)))

			continue;



		if ((link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) && (link->hpd_status == false))

			continue;



		dp_tunnel_settings = get_dp_tunnel_settings(new_ctx, stream);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

+28 −32
Original line number Diff line number Diff line
@@ -48,8 +48,7 @@ 
 */

static bool link_dp_is_bw_alloc_available(struct dc_link *link)

{

	return (link && link->hpd_status

		&& link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

	return (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

		&& link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc

		&& link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);

}
@@ -226,7 +225,6 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) 
	bool ret = false;

	uint8_t val;



	if (link->hpd_status) {

	val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;



	if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
@@ -234,7 +232,9 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) 


		retrieve_usb4_dp_bw_allocation_info(link);



			if (link->dpia_bw_alloc_config.nrd_max_link_rate && link->dpia_bw_alloc_config.nrd_max_lane_count) {

		if (

				link->dpia_bw_alloc_config.nrd_max_link_rate

				&& link->dpia_bw_alloc_config.nrd_max_lane_count) {

			link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate;

			link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count;

		}
@@ -254,7 +254,6 @@ bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link) 
		}

	} else

		DC_LOG_DEBUG("%s:  link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);

	}



	return ret;

}
@@ -297,15 +296,12 @@ void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int pe 
{

	if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling

			&& link->dpia_bw_alloc_config.bw_alloc_enabled) {

		//1. Hot Plug

		if (link->hpd_status && peak_bw > 0) {

		if (peak_bw > 0) {

			// If DP over USB4 then we need to check BW allocation

			link->dpia_bw_alloc_config.link_max_bw = peak_bw;



			link_dpia_send_bw_alloc_request(link, peak_bw);

		}

		//2. Cold Unplug

		else if (!link->hpd_status)

		} else

			dpia_bw_alloc_unplug(link);

	}

}