Unverified Commit d1049fc0 authored by Andy Chiu's avatar Andy Chiu Committed by Palmer Dabbelt
Browse files

riscv: vector: Support calling schedule() for preemptible Vector 



Each function entry implies a call to ftrace infrastructure. And it may
call into schedule in some cases. So, it is possible for preemptible
kernel-mode Vector to implicitly call into schedule. Since all V-regs
are caller-saved, it is possible to drop all V context when a thread
voluntarily call schedule(). Besides, we currently don't pass argument
through vector register, so we don't have to save/restore V-regs in
ftrace trampoline.

Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20250407180838.42877-7-andybnac@gmail.com


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@dabbelt.com>
parent 5aa4ef95

arch/riscv/include/asm/processor.h

+5 −0
Original line number Diff line number Diff line
@@ -79,6 +79,10 @@ struct pt_regs; 
 *       Thus, the task does not own preempt_v. Any use of Vector will have to

 *       save preempt_v, if dirty, and fallback to non-preemptible kernel-mode

 *       Vector.

 *  - bit 29: The thread voluntarily calls schedule() while holding an active

 *    preempt_v. All preempt_v context should be dropped in such case because

 *    V-regs are caller-saved. Only sstatus.VS=ON is persisted across a

 *    schedule() call.

 *  - bit 30: The in-kernel preempt_v context is saved, and requries to be

 *    restored when returning to the context that owns the preempt_v.

 *  - bit 31: The in-kernel preempt_v context is dirty, as signaled by the
@@ -93,6 +97,7 @@ struct pt_regs; 
#define RISCV_PREEMPT_V			0x00000100

#define RISCV_PREEMPT_V_DIRTY		0x80000000

#define RISCV_PREEMPT_V_NEED_RESTORE	0x40000000

#define RISCV_PREEMPT_V_IN_SCHEDULE	0x20000000



/* CPU-specific state of a task */

struct thread_struct {

arch/riscv/include/asm/vector.h

+19 −3
Original line number Diff line number Diff line
@@ -120,6 +120,11 @@ static __always_inline void riscv_v_disable(void) 
		csr_clear(CSR_SSTATUS, SR_VS);

}



static __always_inline bool riscv_v_is_on(void)

{

	return !!(csr_read(CSR_SSTATUS) & SR_VS);

}



static __always_inline void __vstate_csr_save(struct __riscv_v_ext_state *dest)

{

	asm volatile (
@@ -366,6 +371,11 @@ static inline void __switch_to_vector(struct task_struct *prev, 
	struct pt_regs *regs;



	if (riscv_preempt_v_started(prev)) {

		if (riscv_v_is_on()) {

			WARN_ON(prev->thread.riscv_v_flags & RISCV_V_CTX_DEPTH_MASK);

			riscv_v_disable();

			prev->thread.riscv_v_flags |= RISCV_PREEMPT_V_IN_SCHEDULE;

		}

		if (riscv_preempt_v_dirty(prev)) {

			__riscv_v_vstate_save(&prev->thread.kernel_vstate,

					      prev->thread.kernel_vstate.datap);
@@ -376,11 +386,17 @@ static inline void __switch_to_vector(struct task_struct *prev, 
		riscv_v_vstate_save(&prev->thread.vstate, regs);

	}



	if (riscv_preempt_v_started(next))

	if (riscv_preempt_v_started(next)) {

		if (next->thread.riscv_v_flags & RISCV_PREEMPT_V_IN_SCHEDULE) {

			next->thread.riscv_v_flags &= ~RISCV_PREEMPT_V_IN_SCHEDULE;

			riscv_v_enable();

		} else {

			riscv_preempt_v_set_restore(next);

	else

		}

	} else {

		riscv_v_vstate_set_restore(next, task_pt_regs(next));

	}

}



void riscv_v_vstate_ctrl_init(struct task_struct *tsk);

bool riscv_v_vstate_ctrl_user_allowed(void);