Commit d129bce3 authored by Luca Coelho's avatar Luca Coelho
Browse files

drm/i915: move CPT clock gating init into intel_pch 



Move the CPT PCH clock gating programming into
intel_pch_init_clock_gating() and switch the corresponding IVB callers
to the display-specific code.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260324080441.154609-3-luciano.coelho@intel.com


Signed-off-by: default avatarLuca Coelho <luciano.coelho@intel.com>
parent c80c68e7

drivers/gpu/drm/i915/display/intel_pch.c

+40 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <drm/drm_print.h>



#include "intel_de.h"

#include "intel_display.h"

#include "intel_display_regs.h"

#include "intel_display_core.h"

#include "intel_display_utils.h"
@@ -227,12 +228,51 @@ static void intel_pch_ibx_init_clock_gating(struct intel_display *display) 
		       PCH_DPLSUNIT_CLOCK_GATE_DISABLE);

}



static void intel_pch_cpt_init_clock_gating(struct intel_display *display)

{

	enum pipe pipe;

	u32 val;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	intel_de_write(display, SOUTH_DSPCLK_GATE_D,

		       PCH_DPLSUNIT_CLOCK_GATE_DISABLE |

		       PCH_DPLUNIT_CLOCK_GATE_DISABLE |

		       PCH_CPUNIT_CLOCK_GATE_DISABLE);

	intel_de_rmw(display, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);



	/* The below fixes the weird display corruption, a few pixels shifted

	 * downward, on (only) LVDS of some HP laptops with IVY.

	 */

	for_each_pipe(display, pipe) {

		val = intel_de_read(display, TRANS_CHICKEN2(pipe));

		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;

		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;

		if (display->vbt.fdi_rx_polarity_inverted)

			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;

		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;

		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;

		intel_de_write(display, TRANS_CHICKEN2(pipe), val);

	}



	/* WADP0ClockGatingDisable */

	for_each_pipe(display, pipe)

		intel_de_write(display, TRANS_CHICKEN1(pipe),

			       TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

}



void intel_pch_init_clock_gating(struct intel_display *display)

{

	switch (INTEL_PCH_TYPE(display)) {

	case PCH_IBX:

		intel_pch_ibx_init_clock_gating(display);

		break;

	case PCH_CPT:

		intel_pch_cpt_init_clock_gating(display);

		break;

	default:

		break;

	}

drivers/gpu/drm/i915/intel_clock_gating.c

+2 −37
Original line number Diff line number Diff line
@@ -196,41 +196,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *i915) 
	intel_pch_init_clock_gating(i915->display);

}



static void cpt_init_clock_gating(struct drm_i915_private *i915)

{

	struct intel_display *display = i915->display;

	enum pipe pipe;

	u32 val;



	/*

	 * On Ibex Peak and Cougar Point, we need to disable clock

	 * gating for the panel power sequencer or it will fail to

	 * start up when no ports are active.

	 */

	intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |

			   PCH_DPLUNIT_CLOCK_GATE_DISABLE |

			   PCH_CPUNIT_CLOCK_GATE_DISABLE);

	intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);

	/* The below fixes the weird display corruption, a few pixels shifted

	 * downward, on (only) LVDS of some HP laptops with IVY.

	 */

	for_each_pipe(display, pipe) {

		val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));

		val |= TRANS_CHICKEN2_TIMING_OVERRIDE;

		val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;

		if (display->vbt.fdi_rx_polarity_inverted)

			val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;

		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;

		val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;

		intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);

	}

	/* WADP0ClockGatingDisable */

	for_each_pipe(display, pipe) {

		intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),

				   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);

	}

}



static void gen6_check_mch_setup(struct drm_i915_private *i915)

{

	u32 tmp;
@@ -296,7 +261,7 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915) 


	g4x_disable_trickle_feed(i915);



	cpt_init_clock_gating(i915);

	intel_pch_init_clock_gating(i915->display);



	gen6_check_mch_setup(i915);

}
@@ -536,7 +501,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915) 
			 GEN6_MBC_SNPCR_MED);



	if (!HAS_PCH_NOP(display))

		cpt_init_clock_gating(i915);

		intel_pch_init_clock_gating(display);



	gen6_check_mch_setup(i915);

}