Commit d12ed2b7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull phy updates from Vinod Koul:
 "As usual featuring couple of new driver and bunch of new device
  support and some driver changes to Freescale, rockchip driver along
  with couple of yaml binding conversions.

  New Support:
   - Qualcomm IPQ5424 qusb2 support, IPQ5018 uniphy-pcie driver
   - Rockchip usb2 support for RK3562, RK3036 usb2 phy support
   - Samsung exynos2200 eusb2 phy support and driver refactoring for
     this support, exynos7870 USBDRD support
   - Mediatek MT7988 xs-phy support
   - Broadcom BCM74110 usb phy support
   - Renesas RZ/V2H(P) usb2 phy support

  Updates:
   - Freescale phy rate claculation updates, i.MX95 tuning support
   - Better error handling for amlogic pcie phy
   - Rockchip color depth configuration and management support
   - Yaml binding conversion for RK3399 Type-C and PCIe Phy"

* tag 'phy-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits)
  phy: tegra: p2u: Broaden architecture dependency
  phy: rockchip: inno-usb2: Add usb2 phy support for rk3562
  dt-bindings: phy: rockchip,inno-usb2phy: add rk3562
  phy: rockchip: inno-usb2: add phy definition for rk3036
  dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible
  phy: freescale: fsl-samsung-hdmi: Improve LUT search for best clock
  phy: freescale: fsl-samsung-hdmi: Refactor finding PHY settings
  phy: freescale: fsl-samsung-hdmi: Rename phy_clk_round_rate
  phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P)
  phy: renesas: phy-rcar-gen3-usb2: Sort compatible entries by SoC part number
  dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
  dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family
  phy: exynos5-usbdrd: support Exynos USBDRD 3.2 4nm controller
  phy: phy-snps-eusb2: add support for exynos2200
  phy: phy-snps-eusb2: refactor reference clock init
  phy: phy-snps-eusb2: make reset control optional
  phy: phy-snps-eusb2: make repeater optional
  phy: phy-snps-eusb2: split phy init code
  phy: phy-snps-eusb2: refactor constructs names
  phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory
  ...
parents a479ebb2 0c222873
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+4 −1
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties:
      - brcm,bcm4908-usb-phy
      - brcm,bcm7211-usb-phy
      - brcm,bcm7216-usb-phy
      - brcm,bcm74110-usb-phy
      - brcm,brcmstb-usb-phy

  reg:
@@ -139,7 +140,9 @@ allOf:
      properties:
        compatible:
          contains:
            const: brcm,bcm7216-usb-phy
            enum:
              - brcm,bcm7216-usb-phy
              - brcm,bcm74110-usb-phy
    then:
      properties:
        reg:
+32 −5
Original line number Diff line number Diff line
@@ -43,15 +43,15 @@ properties:
  fsl,phy-tx-vref-tune-percent:
    description:
      Tunes the HS DC level relative to the nominal level
    minimum: 94
    minimum: 90
    maximum: 124

  fsl,phy-tx-rise-tune-percent:
    description:
      Adjusts the rise/fall time duration of the HS waveform relative to
      its nominal value
    minimum: 97
    maximum: 103
    minimum: 90
    maximum: 120

  fsl,phy-tx-preemp-amp-tune-microamp:
    description:
@@ -63,8 +63,7 @@ properties:
  fsl,phy-tx-vboost-level-microvolt:
    description:
      Adjust the boosted transmit launch pk-pk differential amplitude
    minimum: 880
    maximum: 1120
    enum: [844, 1008, 1156]

  fsl,phy-comp-dis-tune-percent:
    description:
@@ -112,6 +111,34 @@ allOf:
        reg:
          maxItems: 1

  - if:
      properties:
        compatible:
          enum:
            - fsl,imx8mq-usb-phy
            - fsl,imx8mp-usb-phy
    then:
      properties:
        fsl,phy-tx-vref-tune-percent:
          minimum: 94
        fsl,phy-tx-rise-tune-percent:
          minimum: 97
          maximum: 103

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx95-usb-phy
    then:
      properties:
        fsl,phy-tx-vref-tune-percent:
          maximum: 108
        fsl,phy-comp-dis-tune-percent:
          minimum: 94
          maximum: 104

  - if:
      required:
        - orientation-switch
+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ properties:
          - const: mediatek,mt8173-mipi-tx
      - items:
          - enum:
              - mediatek,mt6893-mipi-tx
              - mediatek,mt8188-mipi-tx
              - mediatek,mt8195-mipi-tx
              - mediatek,mt8365-mipi-tx
+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ properties:
      - items:
          - enum:
              - mediatek,mt2712-tphy
              - mediatek,mt6893-tphy
              - mediatek,mt7629-tphy
              - mediatek,mt7986-tphy
              - mediatek,mt8183-tphy
+16 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ properties:
      - enum:
          - mediatek,mt3611-xsphy
          - mediatek,mt3612-xsphy
          - mediatek,mt7988-xsphy
      - const: mediatek,xsphy

  reg:
@@ -150,6 +151,21 @@ patternProperties:
        minimum: 1
        maximum: 31

      mediatek,syscon-type:
        $ref: /schemas/types.yaml#/definitions/phandle-array
        description:
          A phandle to syscon used to access the register of type switch,
          the field should always be 3 cells long.
        items:
          - items:
              - description:
                  Phandle to phy type configuration system controller
              - description:
                  Phy type configuration register offset
              - description:
                  Index of config segment
                enum: [0, 1, 2, 3]

    required:
      - reg
      - clocks
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