Commit d1624da3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/j721e' 

- Add DT "ti,syscon-acspcie-proxy-ctrl" and driver support to enable the
  ACSPCIE module to drive Refclk for the Endpoint (Siddharth Vadapalli)

- Extract the cadence link setup from cdns_pcie_host_setup() so link setup
  can be done separately during resume (Thomas Richard)

- Use dev_err_probe() to simplify j721e probe (Thomas Richard)

- Add T_PERST_CLK_US definition for the mandatory delay between Refclk
  becoming stable and PERST# being deasserted (Thomas Richard)

- Add j721e suspend and resume support (Théo Lebrun)

* pci/controller/j721e:
  PCI: j721e: Add suspend and resume support
  PCI: j721e: Use T_PERST_CLK_US macro
  PCI: Add T_PERST_CLK_US macro
  PCI: j721e: Add reset GPIO to struct j721e_pcie
  PCI: j721e: Use dev_err_probe() in the probe() function
  PCI: cadence: Set cdns_pcie_host_init() global
  PCI: cadence: Extract link setup sequence from cdns_pcie_host_setup()
  PCI: j721e: Enable ACSPCIE Refclk if "ti,syscon-acspcie-proxy-ctrl" exists
  dt-bindings: PCI: ti,j721e-pci-host: Add ACSPCIE proxy control property
parents f8ca62bf c538d40f

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

+10 −0
Original line number Diff line number Diff line
@@ -38,6 +38,16 @@ properties: 
      - const: reg

      - const: cfg



  ti,syscon-acspcie-proxy-ctrl:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the ACSPCIE Proxy Control Register

          - description: Bitmask corresponding to the PAD IO Buffer

                         output enable fields (Active Low).

    description: Specifier for enabling the ACSPCIE PAD outputs to drive

                 the reference clock to the Endpoint device.



  ti,syscon-pcie-ctrl:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

drivers/pci/controller/cadence/pci-j721e.c

+141 −19
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 
 */



#include <linux/clk.h>

#include <linux/clk-provider.h>

#include <linux/container_of.h>

#include <linux/delay.h>

#include <linux/gpio/consumer.h>

#include <linux/io.h>
@@ -22,6 +24,8 @@ 
#include "../../pci.h"

#include "pcie-cadence.h"



#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)



#define ENABLE_REG_SYS_2	0x108

#define STATUS_REG_SYS_2	0x508

#define STATUS_CLR_REG_SYS_2	0x708
@@ -44,6 +48,7 @@ enum link_status { 
#define J721E_MODE_RC			BIT(7)

#define LANE_COUNT(n)			((n) << 8)



#define ACSPCIE_PAD_DISABLE_MASK	GENMASK(1, 0)

#define GENERATION_SEL_MASK		GENMASK(1, 0)



struct j721e_pcie {
@@ -52,6 +57,7 @@ struct j721e_pcie { 
	u32			mode;

	u32			num_lanes;

	u32			max_lanes;

	struct gpio_desc	*reset_gpio;

	void __iomem		*user_cfg_base;

	void __iomem		*intd_cfg_base;

	u32			linkdown_irq_regfield;
@@ -220,6 +226,36 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 
	return ret;

}



static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie,

				       struct regmap *syscon)

{

	struct device *dev = pcie->cdns_pcie->dev;

	struct device_node *node = dev->of_node;

	u32 mask = ACSPCIE_PAD_DISABLE_MASK;

	struct of_phandle_args args;

	u32 val;

	int ret;



	ret = of_parse_phandle_with_fixed_args(node,

					       "ti,syscon-acspcie-proxy-ctrl",

					       1, 0, &args);

	if (ret) {

		dev_err(dev,

			"ti,syscon-acspcie-proxy-ctrl has invalid arguments\n");

		return ret;

	}



	/* Clear PAD IO disable bits to enable refclk output */

	val = ~(args.args[0]);

	ret = regmap_update_bits(syscon, 0, mask, val);

	if (ret) {

		dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret);

		return ret;

	}



	return 0;

}



static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)

{

	struct device *dev = pcie->cdns_pcie->dev;
@@ -259,7 +295,13 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 
		return ret;

	}



	/* Enable ACSPCIE refclk output if the optional property exists */

	syscon = syscon_regmap_lookup_by_phandle_optional(node,

						"ti,syscon-acspcie-proxy-ctrl");

	if (!syscon)

		return 0;



	return j721e_enable_acspcie_refclk(pcie, syscon);

}



static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
@@ -482,20 +524,20 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
	pm_runtime_enable(dev);

	ret = pm_runtime_get_sync(dev);

	if (ret < 0) {

		dev_err(dev, "pm_runtime_get_sync failed\n");

		dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");

		goto err_get_sync;

	}



	ret = j721e_pcie_ctrl_init(pcie);

	if (ret < 0) {

		dev_err(dev, "pm_runtime_get_sync failed\n");

		dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");

		goto err_get_sync;

	}



	ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,

			       "j721e-pcie-link-down-irq", pcie);

	if (ret < 0) {

		dev_err(dev, "failed to request link state IRQ %d\n", irq);

		dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq);

		goto err_get_sync;

	}
@@ -505,42 +547,40 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
	case PCI_MODE_RC:

		gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);

		if (IS_ERR(gpiod)) {

			ret = PTR_ERR(gpiod);

			if (ret != -EPROBE_DEFER)

				dev_err(dev, "Failed to get reset GPIO\n");

			ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");

			goto err_get_sync;

		}

		pcie->reset_gpio = gpiod;



		ret = cdns_pcie_init_phy(dev, cdns_pcie);

		if (ret) {

			dev_err(dev, "Failed to init phy\n");

			dev_err_probe(dev, ret, "Failed to init phy\n");

			goto err_get_sync;

		}



		clk = devm_clk_get_optional(dev, "pcie_refclk");

		if (IS_ERR(clk)) {

			ret = PTR_ERR(clk);

			dev_err(dev, "failed to get pcie_refclk\n");

			ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");

			goto err_pcie_setup;

		}



		ret = clk_prepare_enable(clk);

		if (ret) {

			dev_err(dev, "failed to enable pcie_refclk\n");

			dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");

			goto err_pcie_setup;

		}

		pcie->refclk = clk;



		/*

		 * "Power Sequencing and Reset Signal Timings" table in

		 * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0

		 * indicates PERST# should be deasserted after minimum of 100us

		 * once REFCLK is stable. The REFCLK to the connector in RC

		 * mode is selected while enabling the PHY. So deassert PERST#

		 * after 100 us.

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 */

		if (gpiod) {

			usleep_range(100, 200);

			fsleep(PCIE_T_PERST_CLK_US);

			gpiod_set_value_cansleep(gpiod, 1);

		}
@@ -554,7 +594,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) 
	case PCI_MODE_EP:

		ret = cdns_pcie_init_phy(dev, cdns_pcie);

		if (ret) {

			dev_err(dev, "Failed to init phy\n");

			dev_err_probe(dev, ret, "Failed to init phy\n");

			goto err_get_sync;

		}
@@ -589,6 +629,87 @@ static void j721e_pcie_remove(struct platform_device *pdev) 
	pm_runtime_disable(dev);

}



static int j721e_pcie_suspend_noirq(struct device *dev)

{

	struct j721e_pcie *pcie = dev_get_drvdata(dev);



	if (pcie->mode == PCI_MODE_RC) {

		gpiod_set_value_cansleep(pcie->reset_gpio, 0);

		clk_disable_unprepare(pcie->refclk);

	}



	cdns_pcie_disable_phy(pcie->cdns_pcie);



	return 0;

}



static int j721e_pcie_resume_noirq(struct device *dev)

{

	struct j721e_pcie *pcie = dev_get_drvdata(dev);

	struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;

	int ret;



	ret = j721e_pcie_ctrl_init(pcie);

	if (ret < 0)

		return ret;



	j721e_pcie_config_link_irq(pcie);



	/*

	 * This is not called explicitly in the probe, it is called by

	 * cdns_pcie_init_phy().

	 */

	ret = cdns_pcie_enable_phy(pcie->cdns_pcie);

	if (ret < 0)

		return ret;



	if (pcie->mode == PCI_MODE_RC) {

		struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);



		ret = clk_prepare_enable(pcie->refclk);

		if (ret < 0)

			return ret;



		/*

		 * The "Power Sequencing and Reset Signal Timings" table of the

		 * PCI Express Card Electromechanical Specification, Revision

		 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#

		 * should be deasserted after minimum of 100us once REFCLK is

		 * stable. The REFCLK to the connector in RC mode is selected

		 * while enabling the PHY. So deassert PERST# after 100 us.

		 */

		if (pcie->reset_gpio) {

			fsleep(PCIE_T_PERST_CLK_US);

			gpiod_set_value_cansleep(pcie->reset_gpio, 1);

		}



		ret = cdns_pcie_host_link_setup(rc);

		if (ret < 0) {

			clk_disable_unprepare(pcie->refclk);

			return ret;

		}



		/*

		 * Reset internal status of BARs to force reinitialization in

		 * cdns_pcie_host_init().

		 */

		for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)

			rc->avail_ib_bar[bar] = true;



		ret = cdns_pcie_host_init(rc);

		if (ret) {

			clk_disable_unprepare(pcie->refclk);

			return ret;

		}

	}



	return 0;

}



static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,

			       j721e_pcie_suspend_noirq,

			       j721e_pcie_resume_noirq);



static struct platform_driver j721e_pcie_driver = {

	.probe  = j721e_pcie_probe,

	.remove_new = j721e_pcie_remove,
@@ -596,6 +717,7 @@ static struct platform_driver j721e_pcie_driver = { 
		.name	= "j721e-pcie",

		.of_match_table = of_j721e_pcie_match,

		.suppress_bind_attrs = true,

		.pm	= pm_sleep_ptr(&j721e_pcie_pm_ops),

	},

};

builtin_platform_driver(j721e_pcie_driver);

drivers/pci/controller/cadence/pcie-cadence-host.c

+28 −16
Original line number Diff line number Diff line
@@ -485,8 +485,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) 
	return cdns_pcie_host_map_dma_ranges(rc);

}



static int cdns_pcie_host_init(struct device *dev,

			       struct cdns_pcie_rc *rc)

int cdns_pcie_host_init(struct cdns_pcie_rc *rc)

{

	int err;
@@ -497,6 +496,30 @@ static int cdns_pcie_host_init(struct device *dev, 
	return cdns_pcie_host_init_address_translation(rc);

}



int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)

{

	struct cdns_pcie *pcie = &rc->pcie;

	struct device *dev = rc->pcie.dev;

	int ret;



	if (rc->quirk_detect_quiet_flag)

		cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);



	cdns_pcie_host_enable_ptm_response(pcie);



	ret = cdns_pcie_start_link(pcie);

	if (ret) {

		dev_err(dev, "Failed to start link\n");

		return ret;

	}



	ret = cdns_pcie_host_start_link(rc);

	if (ret)

		dev_dbg(dev, "PCIe link never came up\n");



	return 0;

}



int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)

{

	struct device *dev = rc->pcie.dev;
@@ -533,25 +556,14 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) 
		return PTR_ERR(rc->cfg_base);

	rc->cfg_res = res;



	if (rc->quirk_detect_quiet_flag)

		cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);



	cdns_pcie_host_enable_ptm_response(pcie);



	ret = cdns_pcie_start_link(pcie);

	if (ret) {

		dev_err(dev, "Failed to start link\n");

		return ret;

	}



	ret = cdns_pcie_host_start_link(rc);

	ret = cdns_pcie_host_link_setup(rc);

	if (ret)

		dev_dbg(dev, "PCIe link never came up\n");

		return ret;



	for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)

		rc->avail_ib_bar[bar] = true;



	ret = cdns_pcie_host_init(dev, rc);

	ret = cdns_pcie_host_init(rc);

	if (ret)

		return ret;

drivers/pci/controller/cadence/pcie-cadence.h

+12 −0
Original line number Diff line number Diff line
@@ -520,10 +520,22 @@ static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) 
}



#ifdef CONFIG_PCIE_CADENCE_HOST

int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc);

int cdns_pcie_host_init(struct cdns_pcie_rc *rc);

int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);

void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,

			       int where);

#else

static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)

{

	return 0;

}



static inline int cdns_pcie_host_init(struct cdns_pcie_rc *rc)

{

	return 0;

}



static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)

{

	return 0;

drivers/pci/pci.h

+16 −1
Original line number Diff line number Diff line
@@ -13,9 +13,24 @@ 


#define PCIE_LINK_RETRAIN_TIMEOUT_MS	1000



/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */

/*

 * Power stable to PERST# inactive.

 *

 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express

 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol

 * "T_PVPERL".

 */

#define PCIE_T_PVPERL_MS		100



/*

 * REFCLK stable before PERST# inactive.

 *

 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express

 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol

 * "T_PERST-CLK".

 */

#define PCIE_T_PERST_CLK_US		100



/*

 * End of conventional reset (PERST# de-asserted) to first configuration

 * request (device able to respond with a "Request Retry Status" completion),