Unverified Commit d1703dc7 authored by Jesse Taube's avatar Jesse Taube Committed by Palmer Dabbelt
Browse files

RISC-V: Detect unaligned vector accesses supported 



Run an unaligned vector access to test if the system supports
vector unaligned access. Add the result to a new key in hwprobe.
This is useful for usermode to know if vector misaligned accesses are
supported and if they are faster or slower than equivalent byte accesses.

Signed-off-by: default avatarJesse Taube <jesse@rivosinc.com>
Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-4-5b33500160f8@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent c05a62c9

arch/riscv/Kconfig

+36 −0
Original line number Diff line number Diff line
@@ -784,12 +784,26 @@ config THREAD_SIZE_ORDER 
	  Specify the Pages of thread stack size (from 4KB to 64KB), which also

	  affects irq stack size, which is equal to thread stack size.



config RISCV_MISALIGNED

	bool

	help

	  Embed support for detecting and emulating misaligned

	  scalar or vector loads and stores.



config RISCV_SCALAR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	select SYSCTL_ARCH_UNALIGN_ALLOW

	help

	  Embed support for emulating misaligned loads and stores.



config RISCV_VECTOR_MISALIGNED

	bool

	select RISCV_MISALIGNED

	depends on RISCV_ISA_V

	help

	  Enable detecting support for vector misaligned loads and stores.



choice

	prompt "Unaligned Accesses Support"

	default RISCV_PROBE_UNALIGNED_ACCESS
@@ -841,6 +855,28 @@ config RISCV_EFFICIENT_UNALIGNED_ACCESS 


endchoice



choice

	prompt "Vector unaligned Accesses Support"

	depends on RISCV_ISA_V

	default RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	help

	  This determines the level of support for vector unaligned accesses. This

	  information is used by the kernel to perform optimizations. It is also

	  exposed to user space via the hwprobe syscall. The hardware will be

	  probed at boot by default.



config RISCV_PROBE_VECTOR_UNALIGNED_ACCESS

	bool "Probe speed of vector unaligned accesses"

	select RISCV_VECTOR_MISALIGNED

	depends on RISCV_ISA_V

	help

	  During boot, the kernel will run a series of tests to determine the

	  speed of vector unaligned accesses if they are supported. This probing

	  will dynamically determine the speed of vector unaligned accesses on

	  the underlying system if they are supported.



endchoice



source "arch/riscv/Kconfig.vendor"



endmenu # "Platform type"

arch/riscv/include/asm/cpufeature.h

+7 −1
Original line number Diff line number Diff line
@@ -59,8 +59,8 @@ void riscv_user_isa_enable(void); 
#define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \

	_RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate)



#if defined(CONFIG_RISCV_SCALAR_MISALIGNED)

bool check_unaligned_access_emulated_all_cpus(void);

#if defined(CONFIG_RISCV_SCALAR_MISALIGNED)

void check_unaligned_access_emulated(struct work_struct *work __always_unused);

void unaligned_emulation_finish(void);

bool unaligned_ctl_available(void);
@@ -72,6 +72,12 @@ static inline bool unaligned_ctl_available(void) 
}

#endif



bool check_vector_unaligned_access_emulated_all_cpus(void);

#if defined(CONFIG_RISCV_VECTOR_MISALIGNED)

void check_vector_unaligned_access_emulated(struct work_struct *work __always_unused);

DECLARE_PER_CPU(long, vector_misaligned_access);

#endif



#if defined(CONFIG_RISCV_PROBE_UNALIGNED_ACCESS)

DECLARE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key);

arch/riscv/include/asm/entry-common.h

+0 −11
Original line number Diff line number Diff line
@@ -25,18 +25,7 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs, 
void handle_page_fault(struct pt_regs *regs);

void handle_break(struct pt_regs *regs);



#ifdef CONFIG_RISCV_SCALAR_MISALIGNED

int handle_misaligned_load(struct pt_regs *regs);

int handle_misaligned_store(struct pt_regs *regs);

#else

static inline int handle_misaligned_load(struct pt_regs *regs)

{

	return -1;

}

static inline int handle_misaligned_store(struct pt_regs *regs)

{

	return -1;

}

#endif



#endif /* _ASM_RISCV_ENTRY_COMMON_H */

arch/riscv/include/asm/hwprobe.h

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ 


#include <uapi/asm/hwprobe.h>



#define RISCV_HWPROBE_MAX_KEY 9

#define RISCV_HWPROBE_MAX_KEY 10



static inline bool riscv_hwprobe_key_is_valid(__s64 key)

{

arch/riscv/include/asm/vector.h

+2 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


extern unsigned long riscv_v_vsize;

int riscv_v_setup_vsize(void);

bool insn_is_vector(u32 insn_buf);

bool riscv_v_first_use_handler(struct pt_regs *regs);

void kernel_vector_begin(void);

void kernel_vector_end(void);
@@ -268,6 +269,7 @@ struct pt_regs; 


static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; }

static __always_inline bool has_vector(void) { return false; }

static __always_inline bool insn_is_vector(u32 insn_buf) { return false; }

static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; }

static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; }

static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; }