Commit d172ea67 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.13-2024-12-11' of... 

Merge tag 'amd-drm-fixes-6.13-2024-12-11' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.13-2024-12-11:

amdgpu:
- ISP hw init fix
- SR-IOV fixes
- Fix contiguous VRAM mapping for UVD on older GPUs
- Fix some regressions due to drm scheduler changes
- Workload profile fixes
- Cleaner shader fix

amdkfd:
- Fix DMA map direction for migration
- Fix a potential null pointer dereference
- Cacheline size fixes
- Runtime PM fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241211215449.741848-1-alexander.deucher@amd.com
parents 4dba1fd3 438b39ac

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+11 −6
Original line number Diff line number Diff line
@@ -1801,13 +1801,18 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 
	if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)

		return -EINVAL;



	/* Make sure VRAM is allocated contigiously */

	(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;

	if ((*bo)->tbo.resource->mem_type == TTM_PL_VRAM &&

	    !((*bo)->tbo.resource->placement & TTM_PL_FLAG_CONTIGUOUS)) {



		amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);

		for (i = 0; i < (*bo)->placement.num_placement; i++)

			(*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;

		r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);

		if (r)

			return r;

	}



	return amdgpu_ttm_alloc_gart(&(*bo)->tbo);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+1 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ const char *amdgpu_asic_name[] = { 
	"LAST",

};



#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMDGPU_MAX_IP_NUM, 0)

#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM  - 1, 0)

/*

 * Default init level where all blocks are expected to be initialized. This is

 * the level of initialization expected by default and also after a full reset

drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c

+2 −0
Original line number Diff line number Diff line
@@ -551,6 +551,8 @@ static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 
	for (i = 0; i < abo->placement.num_placement; ++i) {

		abo->placements[i].fpfn = 0 >> PAGE_SHIFT;

		abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;

		if (abo->placements[i].mem_type == TTM_PL_VRAM)

			abo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;

	}

}

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+7 −6
Original line number Diff line number Diff line
@@ -674,12 +674,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, 
	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&

		ring->funcs->emit_wreg;



	if (adev->gfx.enable_cleaner_shader &&

	    ring->funcs->emit_cleaner_shader &&

	    job->enforce_isolation)

		ring->funcs->emit_cleaner_shader(ring);



	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)

	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync &&

	    !(job->enforce_isolation && !job->vmid))

		return 0;



	amdgpu_ring_ib_begin(ring);
@@ -690,6 +686,11 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, 
	if (need_pipe_sync)

		amdgpu_ring_emit_pipeline_sync(ring);



	if (adev->gfx.enable_cleaner_shader &&

	    ring->funcs->emit_cleaner_shader &&

	    job->enforce_isolation)

		ring->funcs->emit_cleaner_shader(ring);



	if (vm_flush_needed) {

		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);

		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+8 −2
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 
MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin");

MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin");

MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin");



#define GFX9_MEC_HPD_SIZE 4096

#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
@@ -574,6 +576,10 @@ static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 
{

	int err;



	if (amdgpu_sriov_vf(adev))

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,

				"amdgpu/%s_sjt_mec.bin", chip_name);

	else

		err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw,

				"amdgpu/%s_mec.bin", chip_name);

	if (err)