Commit d1c5c3e2 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Fixes for dcn32_clk_mgr implementation 



[Why&How]
Fix CLK MGR early initialization and add logging.

Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321")
Reviewed-by: default avatarLeo Li <sunpeng.li@amd.com>
Reviewed-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1bcdd40

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

+5 −0
Original line number Diff line number Diff line
@@ -878,6 +878,8 @@ void dcn32_clk_mgr_construct( 
		struct pp_smu_funcs *pp_smu,

		struct dccg *dccg)

{

	struct clk_log_info log_info = {0};



	clk_mgr->base.ctx = ctx;

	clk_mgr->base.funcs = &dcn32_funcs;

	if (ASICREV_IS_GC_11_0_2(clk_mgr->base.ctx->asic_id.hw_internal_rev)) {
@@ -911,6 +913,7 @@ void dcn32_clk_mgr_construct( 
			clk_mgr->base.clks.ref_dtbclk_khz = 268750;

	}





	/* integer part is now VCO frequency in kHz */

	clk_mgr->base.dentist_vco_freq_khz = dcn32_get_vco_frequency_from_reg(clk_mgr);
@@ -918,6 +921,8 @@ void dcn32_clk_mgr_construct( 
	if (clk_mgr->base.dentist_vco_freq_khz == 0)

		clk_mgr->base.dentist_vco_freq_khz = 4300000; /* Updated as per HW docs */



	dcn32_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);



	if (ctx->dc->debug.disable_dtb_ref_clk_switch &&

			clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) {

		clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk;