Commit d209124d authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher
Browse files

drm/amd/display: enable HUBP blank behaviour 



- Reverts "drm/amd/display: Revert HUBP blank behaviour for now"
- Hubp blank will fail if the pipe is locked (this is the case on
linux), so add a check to make sure pipe isn't locked, if it is then
defer the blank to post_unlock.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 985faf2c

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+11 −0
Original line number Diff line number Diff line
@@ -659,6 +659,16 @@ void optc1_unlock(struct timing_generator *optc) 
			OTG_MASTER_UPDATE_LOCK, 0);

}



bool optc1_is_locked(struct timing_generator *optc)

{

	struct optc *optc1 = DCN10TG_FROM_TG(optc);

	uint32_t locked;



	REG_GET(OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, &locked);



	return (locked == 1);

}



void optc1_get_position(struct timing_generator *optc,

		struct crtc_position *position)

{
@@ -1513,6 +1523,7 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { 
		.enable_crtc_reset = optc1_enable_crtc_reset,

		.disable_reset_trigger = optc1_disable_reset_trigger,

		.lock = optc1_lock,

		.is_locked = optc1_is_locked,

		.unlock = optc1_unlock,

		.enable_optc_clock = optc1_enable_optc_clock,

		.set_drr = optc1_set_drr,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h

+1 −0
Original line number Diff line number Diff line
@@ -638,6 +638,7 @@ void optc1_set_blank(struct timing_generator *optc, 
		bool enable_blanking);



bool optc1_is_blanked(struct timing_generator *optc);

bool optc1_is_locked(struct timing_generator *optc);



void optc1_program_blank_color(

		struct timing_generator *optc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+8 −0
Original line number Diff line number Diff line
@@ -1765,6 +1765,14 @@ void dcn20_post_unlock_program_front_end( 
		}

	}



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];



		if (pipe->vtp_locked) {

			dc->hwss.set_hubp_blank(dc, pipe, true);

			pipe->vtp_locked = false;

		}

	}

	/* WA to apply WM setting*/

	if (hwseq->wa.DEGVIDCN21)

		dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+21 −2
Original line number Diff line number Diff line
@@ -891,6 +891,25 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc, 
		const struct tg_color *solid_color,

		int width, int height, int offset)

{

	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

			color_space, color_depth, solid_color, width, height, offset);

	struct stream_resource *stream_res = &pipe_ctx->stream_res;



	if (test_pattern != CONTROLLER_DP_TEST_PATTERN_VIDEOMODE) {

		pipe_ctx->vtp_locked = false;

		/* turning on DPG */

		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,

				color_depth, solid_color, width, height, offset);



		/* Defer hubp blank if tg is locked */

		if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) {

			if (stream_res->tg->funcs->is_locked(stream_res->tg))

				pipe_ctx->vtp_locked = true;

			else

				dc->hwss.set_hubp_blank(dc, pipe_ctx, true);

		}

	} else {

		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);

		/* turning off DPG */

		stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space,

				color_depth, solid_color, width, height, offset);

	}

}

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c

+1 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = { 
		.enable_crtc_reset = optc1_enable_crtc_reset,

		.disable_reset_trigger = optc1_disable_reset_trigger,

		.lock = optc3_lock,

		.is_locked = optc1_is_locked,

		.unlock = optc1_unlock,

		.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,

		.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,