Commit d23bd878 authored by Bibo Mao's avatar Bibo Mao Committed by Huacai Chen
Browse files

LoongArch: KVM: Use standard bitops API with eiointc 



Standard bitops APIs such test_bit() is used here, rather than manually
calculating the offset and mask. Also use non-atomic API __set_bit() and
__clear_bit() rather than set_bit() and clear_bit(), since the global
spinlock is held already.

Signed-off-by: default avatarBibo Mao <maobibo@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 9afce1f1

arch/loongarch/kvm/intc/eiointc.c

+11 −16
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ 


static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s)

{

	int ipnum, cpu, cpuid, irq_index, irq_mask, irq;

	int ipnum, cpu, cpuid, irq;

	struct kvm_vcpu *vcpu;



	for (irq = 0; irq < EIOINTC_IRQS; irq++) {
@@ -18,8 +18,6 @@ static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s) 
			ipnum = count_trailing_zeros(ipnum);

			ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;

		}

		irq_index = irq / 32;

		irq_mask = BIT(irq & 0x1f);



		cpuid = s->coremap.reg_u8[irq];

		vcpu = kvm_get_vcpu_by_cpuid(s->kvm, cpuid);
@@ -27,16 +25,16 @@ static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s) 
			continue;



		cpu = vcpu->vcpu_id;

		if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask))

			set_bit(irq, s->sw_coreisr[cpu][ipnum]);

		if (test_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]))

			__set_bit(irq, s->sw_coreisr[cpu][ipnum]);

		else

			clear_bit(irq, s->sw_coreisr[cpu][ipnum]);

			__clear_bit(irq, s->sw_coreisr[cpu][ipnum]);

	}

}



static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level)

{

	int ipnum, cpu, found, irq_index, irq_mask;

	int ipnum, cpu, found;

	struct kvm_vcpu *vcpu;

	struct kvm_interrupt vcpu_irq;
@@ -48,19 +46,16 @@ static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level) 


	cpu = s->sw_coremap[irq];

	vcpu = kvm_get_vcpu(s->kvm, cpu);

	irq_index = irq / 32;

	irq_mask = BIT(irq & 0x1f);



	if (level) {

		/* if not enable return false */

		if (((s->enable.reg_u32[irq_index]) & irq_mask) == 0)

		if (!test_bit(irq, (unsigned long *)s->enable.reg_u32))

			return;

		s->coreisr.reg_u32[cpu][irq_index] |= irq_mask;

		__set_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]);

		found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);

		set_bit(irq, s->sw_coreisr[cpu][ipnum]);

		__set_bit(irq, s->sw_coreisr[cpu][ipnum]);

	} else {

		s->coreisr.reg_u32[cpu][irq_index] &= ~irq_mask;

		clear_bit(irq, s->sw_coreisr[cpu][ipnum]);

		__clear_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]);

		__clear_bit(irq, s->sw_coreisr[cpu][ipnum]);

		found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);

	}
@@ -110,8 +105,8 @@ void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level) 
	unsigned long flags;

	unsigned long *isr = (unsigned long *)s->isr.reg_u8;



	level ? set_bit(irq, isr) : clear_bit(irq, isr);

	spin_lock_irqsave(&s->lock, flags);

	level ? __set_bit(irq, isr) : __clear_bit(irq, isr);

	eiointc_update_irq(s, irq, level);

	spin_unlock_irqrestore(&s->lock, flags);

}