Unverified Commit d25599b5 authored by Alexandre Ghiti's avatar Alexandre Ghiti Committed by Palmer Dabbelt
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dt-bindings: riscv: Add Svvptc ISA extension description 



Add description for the Svvptc ISA extension which was ratified recently.

Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240717060125.139416-3-alexghiti@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent a6efe33c

Documentation/devicetree/bindings/riscv/extensions.yaml

+7 −0
Original line number Diff line number Diff line
@@ -171,6 +171,13 @@ properties: 
            memory types as ratified in the 20191213 version of the privileged

            ISA specification.



        - const: svvptc

          description:

            The standard Svvptc supervisor-level extension for

            address-translation cache behaviour with respect to invalid entries

            as ratified at commit 4a69197e5617 ("Update to ratified state") of

            riscv-svvptc.



        - const: zacas

          description: |

            The Zacas extension for Atomic Compare-and-Swap (CAS) instructions