Commit d289ca74 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.9' of... 

Merge tag 'samsung-clk-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clock driver updates from Krzysztof Kozlowski:

Google GS101:
 - Register the CMU MISC clock controller earlier, so the Multi Core
   Timer clocksource can use it
 - Add PERIC0 and PERIC1 clock controllers

Exynos850:
 - Add PDMA clocks
 - Add CPU cluster 0 and 1 (CMU_CPUCLK0/CMU_CPUCLK1) clock controllers
 - Propagate SPI IPCLK rate change to parents, so the SPI will get
   proper clock rates
 - Refactor the generic Samsung CPU clock controllers code, preparing it
   for supporting Exynos850 CPU clocks

* tag 'samsung-clk-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (25 commits)
  clk: samsung: Add CPU clock support for Exynos850
  clk: samsung: Pass mask to wait_until_mux_stable()
  clk: samsung: Keep register offsets in chip specific structure
  clk: samsung: Keep CPU clock chip specific data in a dedicated struct
  clk: samsung: Pass register layout type explicitly to CLK_CPU()
  clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
  clk: samsung: Group CPU clock functions by chip
  clk: samsung: Use single CPU clock notifier callback for all chips
  clk: samsung: Reduce params count in exynos_register_cpu_clock()
  clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
  clk: samsung: Improve clk-cpu.c style
  dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
  clk: samsung: gs101: add support for cmu_peric1
  clk: samsung: gs101: drop extra empty line
  dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
  clk: samsung: exynos850: Propagate SPI IPCLK rate change
  clk: samsung: gs101: gpio_peric0_pclk needs to be kept on
  clk: samsung: exynos850: Add PDMA clocks
  dt-bindings: clock: tesla,fsd: Fix spelling mistake
  clk: samsung: gs101: add support for cmu_peric0
  ...
parents 6613476e 61f4399c

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

+28 −4
Original line number Diff line number Diff line
@@ -30,14 +30,16 @@ properties: 
      - google,gs101-cmu-top

      - google,gs101-cmu-apm

      - google,gs101-cmu-misc

      - google,gs101-cmu-peric0

      - google,gs101-cmu-peric1



  clocks:

    minItems: 1

    maxItems: 2

    maxItems: 3



  clock-names:

    minItems: 1

    maxItems: 2

    maxItems: 3



  "#clock-cells":

    const: 1
@@ -85,8 +87,30 @@ allOf: 


        clock-names:

          items:

            - const: dout_cmu_misc_bus

            - const: dout_cmu_misc_sss

            - const: bus

            - const: sss



  - if:

      properties:

        compatible:

          contains:

            enum:

              - google,gs101-cmu-peric0

              - google,gs101-cmu-peric1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24.576 MHz)

            - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)

            - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: ip



additionalProperties: false

Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

+42 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ properties: 
      - samsung,exynos850-cmu-aud

      - samsung,exynos850-cmu-cmgp

      - samsung,exynos850-cmu-core

      - samsung,exynos850-cmu-cpucl0

      - samsung,exynos850-cmu-cpucl1

      - samsung,exynos850-cmu-dpu

      - samsung,exynos850-cmu-g3d

      - samsung,exynos850-cmu-hsi
@@ -152,6 +154,46 @@ allOf: 
            - const: dout_core_mmc_embd

            - const: dout_core_sss



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-cpucl0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CPUCL0 switch clock (from CMU_TOP)

            - description: CPUCL0 debug clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_cpucl0_switch

            - const: dout_cpucl0_dbg



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-cpucl1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CPUCL1 switch clock (from CMU_TOP)

            - description: CPUCL1 debug clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_cpucl1_switch

            - const: dout_cpucl1_dbg



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ maintainers: 


description: |

  FSD clock controller consist of several clock management unit

  (CMU), which generates clocks for various inteernal SoC blocks.

  (CMU), which generates clocks for various internal SoC blocks.

  The root clock comes from external OSC clock (24 MHz).



  All available clocks are defined as preprocessor macros in

drivers/clk/samsung/clk-cpu.c

+396 −160

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/samsung/clk-cpu.h

+18 −35
Original line number Diff line number Diff line
@@ -8,7 +8,24 @@ 
#ifndef __SAMSUNG_CLK_CPU_H

#define __SAMSUNG_CLK_CPU_H



#include "clk.h"

/* The CPU clock registers have DIV1 configuration register */

#define CLK_CPU_HAS_DIV1		BIT(0)

/* When ALT parent is active, debug clocks need safe divider values */

#define CLK_CPU_NEEDS_DEBUG_ALT_DIV	BIT(1)



/**

 * enum exynos_cpuclk_layout - CPU clock registers layout compatibility

 * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout

 * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout

 * @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout

 * @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout

 */

enum exynos_cpuclk_layout {

	CPUCLK_LAYOUT_E4210,

	CPUCLK_LAYOUT_E5433,

	CPUCLK_LAYOUT_E850_CL0,

	CPUCLK_LAYOUT_E850_CL1,

};



/**

 * struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
@@ -28,38 +45,4 @@ struct exynos_cpuclk_cfg_data { 
	unsigned long	div1;

};



/**

 * struct exynos_cpuclk - information about clock supplied to a CPU core

 * @hw:		handle between CCF and CPU clock

 * @alt_parent:	alternate parent clock to use when switching the speed

 *		of the primary parent clock

 * @ctrl_base:	base address of the clock controller

 * @lock:	cpu clock domain register access lock

 * @cfg:	cpu clock rate configuration data

 * @num_cfgs:	number of array elements in @cfg array

 * @clk_nb:	clock notifier registered for changes in clock speed of the

 *		primary parent clock

 * @flags:	configuration flags for the CPU clock

 *

 * This structure holds information required for programming the CPU clock for

 * various clock speeds.

 */

struct exynos_cpuclk {

	struct clk_hw				hw;

	const struct clk_hw			*alt_parent;

	void __iomem				*ctrl_base;

	spinlock_t				*lock;

	const struct exynos_cpuclk_cfg_data	*cfg;

	const unsigned long			num_cfgs;

	struct notifier_block			clk_nb;

	unsigned long				flags;



/* The CPU clock registers have DIV1 configuration register */

#define CLK_CPU_HAS_DIV1		(1 << 0)

/* When ALT parent is active, debug clocks need safe divider values */

#define CLK_CPU_NEEDS_DEBUG_ALT_DIV	(1 << 1)

/* The CPU clock registers have Exynos5433-compatible layout */

#define CLK_CPU_HAS_E5433_REGS_LAYOUT	(1 << 2)

};



#endif /* __SAMSUNG_CLK_CPU_H */