Commit d2bcca0c authored by Neil Armstrong's avatar Neil Armstrong Committed by Rob Clark
Browse files

drm/msm: add support for A750 GPU 



Add support for the A750 GPU found on the SM8650 platform

Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU
doesn't have an HWCFG block but a separate register set.

The A750 GPU info are added under the adreno_is_a750() macro and
the ADRENO_7XX_GEN3 family id.

Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578693/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 1fdd35d5

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+2 −0
Original line number Diff line number Diff line
@@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) 
		 */

		if (adreno_is_a740(adreno_gpu))

			chipid_min = 2;

		else if (adreno_is_a750(adreno_gpu))

			chipid_min = 9;

		else

			return -EINVAL;

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+25 −3
Original line number Diff line number Diff line
@@ -961,7 +961,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
	unsigned int i;

	u32 val, clock_cntl_on, cgc_mode;



	if (!adreno_gpu->info->hwcg)

	if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu)))

		return;



	if (adreno_is_a630(adreno_gpu))
@@ -982,6 +982,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) 
			  state ? 0x5555 : 0);

	}



	if (!adreno_gpu->info->hwcg) {

		gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);

		gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0);



		if (state) {

			gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1);



			if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val,

					     val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) {

				dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n");

				return;

			}



			gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0);

		}



		return;

	}



	val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);



	/* Don't re-program the registers if they are already correct */
@@ -1239,7 +1258,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) 
		count = ARRAY_SIZE(a660_protect);

		count_max = 48;

		BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);

	} else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) {

	} else if (adreno_is_a730(adreno_gpu) ||

		   adreno_is_a740(adreno_gpu) ||

		   adreno_is_a750(adreno_gpu)) {

		regs = a730_protect;

		count = ARRAY_SIZE(a730_protect);

		count_max = 48;
@@ -2879,7 +2900,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) 


	/* gpu->info only gets assigned in adreno_gpu_init() */

	is_a7xx = config->info->family == ADRENO_7XX_GEN1 ||

		  config->info->family == ADRENO_7XX_GEN2;

		  config->info->family == ADRENO_7XX_GEN2 ||

		  config->info->family == ADRENO_7XX_GEN3;



	a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);

drivers/gpu/drm/msm/adreno/adreno_device.c

+14 −0
Original line number Diff line number Diff line
@@ -550,6 +550,20 @@ static const struct adreno_info gpulist[] = { 
		.zapfw = "a740_zap.mdt",

		.hwcg = a740_hwcg,

		.address_space_size = SZ_16G,

	}, {

		.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */

		.family = ADRENO_7XX_GEN3,

		.fw = {

			[ADRENO_FW_SQE] = "gen70900_sqe.fw",

			[ADRENO_FW_GMU] = "gmu_gen70900.bin",

		},

		.gmem = 3 * SZ_1M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |

			  ADRENO_QUIRK_HAS_HW_APRIV,

		.init = a6xx_gpu_init,

		.zapfw = "gen70900_zap.mbn",

		.address_space_size = SZ_16G,

	},

};

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+8 −2
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ enum adreno_family { 
	ADRENO_6XX_GEN4,  /* a660 family */

	ADRENO_7XX_GEN1,  /* a730 family */

	ADRENO_7XX_GEN2,  /* a740 family */

	ADRENO_7XX_GEN3,  /* a750 family */

};



#define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
@@ -428,12 +429,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) 
	return gpu->info->chip_ids[0] == 0x43050a01;

}



/* Placeholder to make future diffs smaller */

static inline int adreno_is_a750(struct adreno_gpu *gpu)

{

	return gpu->info->chip_ids[0] == 0x43051401;

}



static inline int adreno_is_a740_family(struct adreno_gpu *gpu)

{

	if (WARN_ON_ONCE(!gpu->info))

		return false;

	return gpu->info->family == ADRENO_7XX_GEN2;

	return gpu->info->family == ADRENO_7XX_GEN2 ||

	       gpu->info->family == ADRENO_7XX_GEN3;

}



static inline int adreno_is_a7xx(struct adreno_gpu *gpu)