Commit d2f7f1ba authored by Shuijing Li's avatar Shuijing Li Committed by Chun-Kuang Hu
Browse files

drm/mediatek: dp: Add the audio divider to mtk_dp_data struct 



Due to the difference of HW, different dividers need to be set.

Signed-off-by: default avatarShuijing Li <shuijing.li@mediatek.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20230822024155.26670-4-shuijing.li@mediatek.com/


Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent 2d503773

drivers/gpu/drm/mediatek/mtk_dp.c

+4 −1
Original line number Diff line number Diff line
@@ -142,6 +142,7 @@ struct mtk_dp_data { 
	const struct mtk_dp_efuse_fmt *efuse_fmt;

	bool audio_supported;

	bool audio_pkt_in_hblank_area;

	u16 audio_m_div2_bit;

};



static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
@@ -650,7 +651,7 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp, 
static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)

{

	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,

			   AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,

			   mtk_dp->data->audio_m_div2_bit,

			   AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);

}
@@ -2755,6 +2756,7 @@ static const struct mtk_dp_data mt8195_edp_data = { 
	.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,

	.efuse_fmt = mt8195_edp_efuse_fmt,

	.audio_supported = false,

	.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,

};



static const struct mtk_dp_data mt8195_dp_data = {
@@ -2762,6 +2764,7 @@ static const struct mtk_dp_data mt8195_dp_data = { 
	.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,

	.efuse_fmt = mt8195_dp_efuse_fmt,

	.audio_supported = true,

	.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,

};



static const struct of_device_id mtk_dp_of_match[] = {

drivers/gpu/drm/mediatek/mtk_dp_reg.h

+6 −6
Original line number Diff line number Diff line
@@ -159,12 +159,12 @@ 
#define MTK_DP_ENC0_P0_30BC			0x30bc

#define ISRC_CONT_DP_ENC0_P0				BIT(0)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK	GENMASK(10, 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2	(1 << 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4	(2 << 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8	(3 << 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2	(5 << 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4	(6 << 8)

#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8	(7 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2	(1 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4	(2 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_8	(3 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2	(5 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4	(6 << 8)

#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8	(7 << 8)

#define MTK_DP_ENC0_P0_30D8			0x30d8

#define MTK_DP_ENC0_P0_312C			0x312c

#define ASP_HB2_DP_ENC0_P0_MASK				GENMASK(7, 0)