Commit d32ce5ab authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-misc-next-2023-10-12' of git://anongit.freedesktop.org/drm/drm-misc into drm-next



drm-misc-next for v6.7-rc1:

Contains the previous pull request drm-misc-next-2023-10-06 + following:

Cross-subsystem Changes:
- Rename fb_pgprot to pgprot_framebuffer and remove file argument/
- Update iosys-map documentation typos.

Core Changes:
- Assorted fixes to drm/panel.
- Add HPD state to drm_connector_oob_hotplug_event(), and implement
  oob hotplug events in bridge connector.
- Replace drm_framebuffer_plane_width/height  with calls to
  drm_format_info_plane_width/height.

Driver Changes:
- Clock and debug fixes for bridge/samsung-dsim.
- More btree -> maple tree conversions.
- Assorted bugfixes in rockchip, panel-tpo-tpg110,
- Add LTK050H3148W-CTA6 panel support.
- Assorted small fixes in host1x, tegra, simpledrm.
- Suspend fixes for host1x.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3812345e-b086-4d72-8504-f58d84e8feab@linux.intel.com
parents 389af786 c395c83a
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/lvds-data-mapping.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LVDS Data Mapping

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |
  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
  incompatible data link layers have been used over time to transmit image data
  to LVDS devices. This bindings supports devices compatible with the following
  specifications.

  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
  Semiconductor
  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
  Electronics Standards Association (VESA)

  Device compatible with those specifications have been marketed under the
  FPD-Link and FlatLink brands.

properties:
  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - vesa-24
    description: |
      The color signals mapping order.

      LVDS data mappings are defined as follows.

      - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
        [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><

      - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
        specifications. Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
        Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><

      Control signals are mapped as follows.

      CTL0: HSync
      CTL1: VSync
      CTL2: Data Enable
      CTL3: 0

additionalProperties: true

...
+9 −68
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@@ -6,83 +6,24 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#

title: LVDS Display Common Properties

allOf:
  - $ref: lvds-data-mapping.yaml#

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |+
  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
  incompatible data link layers have been used over time to transmit image data
  to LVDS devices. This bindings supports devices compatible with the following
  specifications.

  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
  Semiconductor
  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
  Electronics Standards Association (VESA)

  Device compatible with those specifications have been marketed under the
  FPD-Link and FlatLink brands.
description:
  This binding extends the data mapping defined in lvds-data-mapping.yaml.
  It supports reversing the bit order on the formats defined there in order
  to accomodate for even more specialized data formats, since a variety of
  data formats and layouts is used to drive LVDS displays.

properties:
  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - vesa-24
    description: |
      The color signals mapping order.

      LVDS data mappings are defined as follows.

      - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
        [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><

      - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
        specifications. Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
        Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><

      Control signals are mapped as follows.

      CTL0: HSync
      CTL1: VSync
      CTL2: Data Enable
      CTL3: 0

  data-mirror:
    type: boolean
    description:
      If set, reverse the bit order described in the data mappings below on all
      If set, reverse the bit order described in the data mappings on all
      data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.

additionalProperties: true
+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ properties:
    enum:
      - leadtek,ltk050h3146w
      - leadtek,ltk050h3146w-a2
      - leadtek,ltk050h3148w
  reg: true
  backlight: true
  reset-gpios: true
+2 −3
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@@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NewVision NV3051D based LCD panel

description: |
  The NewVision NV3051D is a driver chip used to drive DSI panels. For now,
  this driver only supports the 640x480 panels found in the Anbernic RG353
  based devices.
  The NewVision NV3051D is a driver chip used to drive DSI panels.

maintainers:
  - Chris Morgan <macromorgan@hotmail.com>
@@ -21,6 +19,7 @@ properties:
  compatible:
    items:
      - enum:
          - anbernic,rg351v-panel
          - anbernic,rg353p-panel
          - anbernic,rg353v-panel
      - const: newvision,nv3051d
+25 −1
Original line number Diff line number Diff line
@@ -21,9 +21,9 @@ description: |

allOf:
  - $ref: panel-common.yaml#
  - $ref: ../lvds-data-mapping.yaml#

properties:

  compatible:
    enum:
    # compatible must be listed in alphabetical order, ordered by compatible.
@@ -359,6 +359,17 @@ properties:
  power-supply: true
  no-hpd: true
  hpd-gpios: true
  data-mapping: true

if:
  not:
    properties:
      compatible:
        contains:
          const: innolux,g101ice-l01
then:
  properties:
    data-mapping: false

additionalProperties: false

@@ -378,3 +389,16 @@ examples:
        };
      };
    };
  - |
    panel_lvds: panel-lvds {
      compatible = "innolux,g101ice-l01";
      power-supply = <&vcc_lcd_reg>;

      data-mapping = "jeida-24";

      port {
        panel_in_lvds: endpoint {
          remote-endpoint = <&ltdc_out_lvds>;
        };
      };
    };
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