Commit d33050ae authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted'... 

Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted' and 'clk-qcom' into clk-next

 - Add consumer info to clk debugfs
 - Fix various clk drivers that have clk_hw_onecell_data not at the end
   of an allocation

* clk-debugfs:
  clk: Allow phase adjustment from debugfs
  clk: Show active consumers of clocks in debugfs

* clk-spreadtrum:
  clk: sprd: Composite driver support offset config

* clk-sifive:
  clk: sifive: Allow building the driver as a module
  clk: analogbits: Allow building the library as a module

* clk-counted:
  clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data
  clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data
  clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider
  clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider

* clk-qcom: (36 commits)
  clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
  clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
  clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
  clk: qcom: gcc-ipq6018: add QUP6 I2C clock
  clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll
  clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config
  clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll
  clk: qcom: clk-alpha-pll: introduce stromer plus ops
  clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
  clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure
  clk: qcom: Replace of_device.h with explicit includes
  clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect
  clk: qcom: cbf-msm8996: Convert to platform remove callback returning void
  clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
  clk: qcom: Add GCC driver support for SM4450
  dt-bindings: clock: qcom: Add GCC clocks for SM4450
  ...
parents 702a582b e43d3191 48a8748f c8e1d8ae 65f9e1be 0dea4e30

Documentation/devicetree/bindings/clock/qcom,hfpll.txt

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@@ -12,6 +12,9 @@ PROPERTIES 
                        "qcom,hfpll-apq8064", "qcom,hfpll"

                        "qcom,hfpll-msm8974", "qcom,hfpll"

                        "qcom,hfpll-msm8960", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a53", "qcom,hfpll"

                        "qcom,msm8976-hfpll-a72", "qcom,hfpll"

                        "qcom,msm8976-hfpll-cci", "qcom,hfpll"



- reg:

	Usage: required

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -28,6 +28,7 @@ properties: 
      - qcom,sdx55-rpmh-clk

      - qcom,sdx65-rpmh-clk

      - qcom,sdx75-rpmh-clk

      - qcom,sm4450-rpmh-clk

      - qcom,sm6350-rpmh-clk

      - qcom,sm8150-rpmh-clk

      - qcom,sm8250-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm4450-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on SM4450



maintainers:

  - Ajit Pandey <quic_ajipan@quicinc.com>

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on SM4450



  See also:: include/dt-bindings/clock/qcom,sm4450-gcc.h



properties:

  compatible:

    const: qcom,sm4450-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,sm4450-gcc";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,

               <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,

               <&ufs_mem_phy 2>, <&usb_1_qmpphy>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

+6 −2
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@@ -13,11 +13,15 @@ description: | 
  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SM8450.



  See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h

  See also::

    include/dt-bindings/clock/qcom,sm8450-camcc.h

    include/dt-bindings/clock/qcom,sm8550-camcc.h



properties:

  compatible:

    const: qcom,sm8450-camcc

    enum:

      - qcom,sm8450-camcc

      - qcom,sm8550-camcc



  clocks:

    items:

drivers/clk/analogbits/Kconfig

+1 −1
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# SPDX-License-Identifier: GPL-2.0-only

config CLK_ANALOGBITS_WRPLL_CLN28HPC

	bool
 
	tristate