Commit d36bdd77 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Implement w/a 22010492432 for adl-s 



adl-s needs the combo PLL DCO fraction w/a as well.
Gets us slightly more accurate clock out of the PLL.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220613201439.23341-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent a50cc495

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+2 −2
Original line number Diff line number Diff line
@@ -2459,7 +2459,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params, 
}



/*

 * Display WA #22010492432: ehl, tgl, adl-p

 * Display WA #22010492432: ehl, tgl, adl-s, adl-p

 * Program half of the nominal DCO divider fraction value.

 */

static bool
@@ -2467,7 +2467,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) 
{

	return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&

		 IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||

		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) &&

		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&

		 i915->dpll.ref_clks.nssc == 38400;

}