Commit d3979192 authored by Ayushi Makhija's avatar Ayushi Makhija Committed by Dmitry Baryshkov
Browse files

drm/msm/dsi: add DSI PHY configuration on SA8775P 



The SA8775P SoC uses the 5nm (v4.2) DSI PHY driver with
different enable regulator load.

Signed-off-by: default avatarAyushi Makhija <quic_amakhija@quicinc.com>
Reviewed-by: default avatarDmitry Baryshkov <lumag@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/649842/
Link: https://lore.kernel.org/r/20250424062431.2040692-5-quic_amakhija@quicinc.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent a6f2524f

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
	  .data = &dsi_phy_7nm_cfgs },

	{ .compatible = "qcom,dsi-phy-7nm-8150",

	  .data = &dsi_phy_7nm_8150_cfgs },

	{ .compatible = "qcom,sa8775p-dsi-phy-5nm",

	  .data = &dsi_phy_5nm_8775p_cfgs },

	{ .compatible = "qcom,sar2130p-dsi-phy-5nm",

	  .data = &dsi_phy_5nm_sar2130p_cfgs },

	{ .compatible = "qcom,sc7280-dsi-phy-7nm",

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+27 −0
Original line number Diff line number Diff line
@@ -1147,6 +1147,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_37750uA_regulators[] = { 
	{ .supply = "vdds", .init_load_uA = 37550 },

};



static const struct regulator_bulk_data dsi_phy_7nm_48000uA_regulators[] = {

	{ .supply = "vdds", .init_load_uA = 48000 },

};



static const struct regulator_bulk_data dsi_phy_7nm_98000uA_regulators[] = {

	{ .supply = "vdds", .init_load_uA = 98000 },

};
@@ -1289,6 +1293,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { 
	.quirks = DSI_PHY_7NM_QUIRK_V4_3,

};



const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_48000uA_regulators,

	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_48000uA_regulators),

	.ops = {

		.enable = dsi_7nm_phy_enable,

		.disable = dsi_7nm_phy_disable,

		.pll_init = dsi_pll_7nm_init,

		.save_pll_state = dsi_7nm_pll_save_state,

		.restore_pll_state = dsi_7nm_pll_restore_state,

		.set_continuous_clock = dsi_7nm_set_continuous_clock,

		},

	.min_pll_rate = 600000000UL,

#ifdef CONFIG_64BIT

	.max_pll_rate = 5000000000UL,

#else

	.max_pll_rate = ULONG_MAX,

#endif

	.io_start = { 0xae94400, 0xae96400 },

	.num_dsi_phy = 2,

	.quirks = DSI_PHY_7NM_QUIRK_V4_2,

};



const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_97800uA_regulators,