Commit d3c16475 authored by Hongguang Gao's avatar Hongguang Gao Committed by Jakub Kicinski
Browse files

bnxt_en: Consolidate DB offset calculation



The doorbell offset on P5 chips is hard coded.  On the new P7 chips,
it is returned by the firmware.  Simplify the logic that determines
this offset and store it in a new db_offset field in struct bnxt.
Also, provide this offset to the RoCE driver in struct bnxt_en_dev.

Reviewed-by: default avatarKalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: default avatarHongguang Gao <hongguang.gao@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Link: https://lore.kernel.org/r/20231201223924.26955-5-michael.chan@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent a432a45b
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+7 −9
Original line number Diff line number Diff line
@@ -6031,10 +6031,6 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
			u32 map_idx, u32 xid)
{
	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
		if (BNXT_PF(bp))
			db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
		else
			db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
		switch (ring_type) {
		case HWRM_RING_ALLOC_TX:
			db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
@@ -6054,6 +6050,8 @@ static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,

		if (bp->flags & BNXT_FLAG_CHIP_P7)
			db->db_key64 |= DBR_VALID;

		db->doorbell = bp->bar1 + bp->db_offset;
	} else {
		db->doorbell = bp->bar1 + map_idx * 0x80;
		switch (ring_type) {
@@ -7146,7 +7144,6 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
{
	struct hwrm_func_qcfg_output *resp;
	struct hwrm_func_qcfg_input *req;
	u32 min_db_offset = 0;
	u16 flags;
	int rc;

@@ -7204,16 +7201,17 @@ static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
	if (bp->db_size)
		goto func_qcfg_exit;

	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
	bp->db_offset = le16_to_cpu(resp->legacy_l2_db_size_kb) * 1024;
	if (BNXT_CHIP_P5(bp)) {
		if (BNXT_PF(bp))
			min_db_offset = DB_PF_OFFSET_P5;
			bp->db_offset = DB_PF_OFFSET_P5;
		else
			min_db_offset = DB_VF_OFFSET_P5;
			bp->db_offset = DB_VF_OFFSET_P5;
	}
	bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
				 1024);
	if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
	    bp->db_size <= min_db_offset)
	    bp->db_size <= bp->db_offset)
		bp->db_size = pci_resource_len(bp->pdev, 2);

func_qcfg_exit:
+1 −0
Original line number Diff line number Diff line
@@ -2216,6 +2216,7 @@ struct bnxt {
	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
	spinlock_t		db_lock;
#endif
	int			db_offset;	/* db_offset within db_size */
	int			db_size;

#define BNXT_NTP_FLTR_MAX_FLTR	4096
+4 −6
Original line number Diff line number Diff line
@@ -42,15 +42,12 @@ static void bnxt_fill_msix_vecs(struct bnxt *bp, struct bnxt_msix_entry *ent)
	for (i = 0; i < num_msix; i++) {
		ent[i].vector = bp->irq_tbl[idx + i].vector;
		ent[i].ring_idx = idx + i;
		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
			ent[i].db_offset = DB_PF_OFFSET_P5;
			if (BNXT_VF(bp))
				ent[i].db_offset = DB_VF_OFFSET_P5;
		} else {
		if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS)
			ent[i].db_offset = bp->db_offset;
		else
			ent[i].db_offset = (idx + i) * 0x80;
	}
}
}

int bnxt_register_dev(struct bnxt_en_dev *edev,
		      struct bnxt_ulp_ops *ulp_ops,
@@ -333,6 +330,7 @@ static void bnxt_set_edev_info(struct bnxt_en_dev *edev, struct bnxt *bp)
	edev->pdev = bp->pdev;
	edev->l2_db_size = bp->db_size;
	edev->l2_db_size_nc = bp->db_size;
	edev->l2_db_offset = bp->db_offset;

	if (bp->flags & BNXT_FLAG_ROCEV1_CAP)
		edev->flags |= BNXT_EN_FLAG_ROCEV1_CAP;
+4 −0
Original line number Diff line number Diff line
@@ -73,6 +73,10 @@ struct bnxt_en_dev {
							 * bytes mapped as non-
							 * cacheable.
							 */
	int				l2_db_offset;	/* Doorbell offset in
							 * bytes within
							 * l2_db_size_nc.
							 */
	u16				chip_num;
	u16				hw_ring_stats_size;
	u16				pf_port_id;