Commit d3f0bec2 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/rockchip' 

- Add struct rockchip_pcie_ep kernel-doc to fix warnings (Damien Le Moal)

- Simplify clock and reset handling by using bulk interfaces (Anand Moon)

- Pass typed rockchip_pcie (not void) pointer to
  rockchip_pcie_disable_clocks() (Anand Moon)

- Return -ENOMEM, not success, when pci_epc_mem_alloc_addr() fails (Dan
  Carpenter)

* pci/controller/rockchip:
  PCI: rockchip-ep: Fix error code in rockchip_pcie_ep_init_ob_mem()
  PCI: rockchip: Refactor rockchip_pcie_disable_clocks() signature
  PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
  PCI: rockchip: Simplify clock handling by using clk_bulk*() functions
  PCI: rockchip: Add missing fields descriptions for struct rockchip_pcie_ep
parents a306f01e 7ca28876

drivers/pci/controller/pcie-rockchip-ep.c

+5 −0
Original line number Diff line number Diff line
@@ -40,6 +40,10 @@ 
 * @irq_pci_fn: the latest PCI function that has updated the mapping of

 *		the MSI/INTX IRQ dedicated outbound region.

 * @irq_pending: bitmask of asserted INTX IRQs.

 * @perst_irq: IRQ used for the PERST# signal.

 * @perst_asserted: True if the PERST# signal was asserted.

 * @link_up: True if the PCI link is up.

 * @link_training: Work item to execute PCI link training.

 */

struct rockchip_pcie_ep {

	struct rockchip_pcie	rockchip;
@@ -784,6 +788,7 @@ static int rockchip_pcie_ep_init_ob_mem(struct rockchip_pcie_ep *ep) 
						  SZ_1M);

	if (!ep->irq_cpu_addr) {

		dev_err(dev, "failed to reserve memory space for MSI\n");

		err = -ENOMEM;

		goto err_epc_mem_exit;

	}

drivers/pci/controller/pcie-rockchip.c

+37 −182
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 
	struct platform_device *pdev = to_platform_device(dev);

	struct device_node *node = dev->of_node;

	struct resource *regs;

	int err;

	int err, i;



	if (rockchip->is_rc) {

		regs = platform_get_resource_byname(pdev,
@@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 
	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)

		rockchip->link_gen = 2;



	rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");

	if (IS_ERR(rockchip->core_rst)) {

		if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing core reset property in node\n");

		return PTR_ERR(rockchip->core_rst);

	}



	rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");

	if (IS_ERR(rockchip->mgmt_rst)) {

		if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing mgmt reset property in node\n");

		return PTR_ERR(rockchip->mgmt_rst);

	}

	for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++)

		rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i];



	rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,

								"mgmt-sticky");

	if (IS_ERR(rockchip->mgmt_sticky_rst)) {

		if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing mgmt-sticky reset property in node\n");

		return PTR_ERR(rockchip->mgmt_sticky_rst);

	}

	err = devm_reset_control_bulk_get_exclusive(dev,

						    ROCKCHIP_NUM_PM_RSTS,

						    rockchip->pm_rsts);

	if (err)

		return dev_err_probe(dev, err, "Cannot get the PM reset\n");



	rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");

	if (IS_ERR(rockchip->pipe_rst)) {

		if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing pipe reset property in node\n");

		return PTR_ERR(rockchip->pipe_rst);

	}

	for (i = 0; i < ROCKCHIP_NUM_CORE_RSTS; i++)

		rockchip->core_rsts[i].id = rockchip_pci_core_rsts[i];



	rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");

	if (IS_ERR(rockchip->pm_rst)) {

		if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing pm reset property in node\n");

		return PTR_ERR(rockchip->pm_rst);

	}



	rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");

	if (IS_ERR(rockchip->pclk_rst)) {

		if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing pclk reset property in node\n");

		return PTR_ERR(rockchip->pclk_rst);

	}



	rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");

	if (IS_ERR(rockchip->aclk_rst)) {

		if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)

			dev_err(dev, "missing aclk reset property in node\n");

		return PTR_ERR(rockchip->aclk_rst);

	}

	err = devm_reset_control_bulk_get_exclusive(dev,

						    ROCKCHIP_NUM_CORE_RSTS,

						    rockchip->core_rsts);

	if (err)

		return dev_err_probe(dev, err, "Cannot get the Core resets\n");



	if (rockchip->is_rc)

		rockchip->perst_gpio = devm_gpiod_get_optional(dev, "ep",
@@ -129,29 +97,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) 
		return dev_err_probe(dev, PTR_ERR(rockchip->perst_gpio),

				     "failed to get PERST# GPIO\n");



	rockchip->aclk_pcie = devm_clk_get(dev, "aclk");

	if (IS_ERR(rockchip->aclk_pcie)) {

		dev_err(dev, "aclk clock not found\n");

		return PTR_ERR(rockchip->aclk_pcie);

	}



	rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");

	if (IS_ERR(rockchip->aclk_perf_pcie)) {

		dev_err(dev, "aclk_perf clock not found\n");

		return PTR_ERR(rockchip->aclk_perf_pcie);

	}



	rockchip->hclk_pcie = devm_clk_get(dev, "hclk");

	if (IS_ERR(rockchip->hclk_pcie)) {

		dev_err(dev, "hclk clock not found\n");

		return PTR_ERR(rockchip->hclk_pcie);

	}



	rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");

	if (IS_ERR(rockchip->clk_pcie_pm)) {

		dev_err(dev, "pm clock not found\n");

		return PTR_ERR(rockchip->clk_pcie_pm);

	}

	rockchip->num_clks = devm_clk_bulk_get_all(dev, &rockchip->clks);

	if (rockchip->num_clks < 0)

		return dev_err_probe(dev, rockchip->num_clks,

				     "failed to get clocks\n");



	return 0;

}
@@ -169,23 +118,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
	int err, i;

	u32 regs;



	err = reset_control_assert(rockchip->aclk_rst);

	if (err) {

		dev_err(dev, "assert aclk_rst err %d\n", err);

		return err;

	}



	err = reset_control_assert(rockchip->pclk_rst);

	if (err) {

		dev_err(dev, "assert pclk_rst err %d\n", err);

		return err;

	}



	err = reset_control_assert(rockchip->pm_rst);

	if (err) {

		dev_err(dev, "assert pm_rst err %d\n", err);

		return err;

	}

	err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS,

					rockchip->pm_rsts);

	if (err)

		return dev_err_probe(dev, err, "Couldn't assert PM resets\n");



	for (i = 0; i < MAX_LANE_NUM; i++) {

		err = phy_init(rockchip->phys[i]);
@@ -195,47 +131,19 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
		}

	}



	err = reset_control_assert(rockchip->core_rst);

	if (err) {

		dev_err(dev, "assert core_rst err %d\n", err);

		goto err_exit_phy;

	}



	err = reset_control_assert(rockchip->mgmt_rst);

	if (err) {

		dev_err(dev, "assert mgmt_rst err %d\n", err);

		goto err_exit_phy;

	}



	err = reset_control_assert(rockchip->mgmt_sticky_rst);

	if (err) {

		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);

		goto err_exit_phy;

	}



	err = reset_control_assert(rockchip->pipe_rst);

	err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS,

					rockchip->core_rsts);

	if (err) {

		dev_err(dev, "assert pipe_rst err %d\n", err);

		dev_err_probe(dev, err, "Couldn't assert Core resets\n");

		goto err_exit_phy;

	}



	udelay(10);



	err = reset_control_deassert(rockchip->pm_rst);

	err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS,

					  rockchip->pm_rsts);

	if (err) {

		dev_err(dev, "deassert pm_rst err %d\n", err);

		goto err_exit_phy;

	}



	err = reset_control_deassert(rockchip->aclk_rst);

	if (err) {

		dev_err(dev, "deassert aclk_rst err %d\n", err);

		goto err_exit_phy;

	}



	err = reset_control_deassert(rockchip->pclk_rst);

	if (err) {

		dev_err(dev, "deassert pclk_rst err %d\n", err);

		dev_err(dev, "Couldn't deassert PM resets %d\n", err);

		goto err_exit_phy;

	}
@@ -275,31 +183,10 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) 
		goto err_power_off_phy;

	}



	/*

	 * Please don't reorder the deassert sequence of the following

	 * four reset pins.

	 */

	err = reset_control_deassert(rockchip->mgmt_sticky_rst);

	if (err) {

		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);

		goto err_power_off_phy;

	}



	err = reset_control_deassert(rockchip->core_rst);

	err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS,

					  rockchip->core_rsts);

	if (err) {

		dev_err(dev, "deassert core_rst err %d\n", err);

		goto err_power_off_phy;

	}



	err = reset_control_deassert(rockchip->mgmt_rst);

	if (err) {

		dev_err(dev, "deassert mgmt_rst err %d\n", err);

		goto err_power_off_phy;

	}



	err = reset_control_deassert(rockchip->pipe_rst);

	if (err) {

		dev_err(dev, "deassert pipe_rst err %d\n", err);

		dev_err(dev, "Couldn't deassert Core reset %d\n", err);

		goto err_power_off_phy;

	}
@@ -375,50 +262,18 @@ int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip) 
	struct device *dev = rockchip->dev;

	int err;



	err = clk_prepare_enable(rockchip->aclk_pcie);

	if (err) {

		dev_err(dev, "unable to enable aclk_pcie clock\n");

		return err;

	}



	err = clk_prepare_enable(rockchip->aclk_perf_pcie);

	if (err) {

		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");

		goto err_aclk_perf_pcie;

	}



	err = clk_prepare_enable(rockchip->hclk_pcie);

	if (err) {

		dev_err(dev, "unable to enable hclk_pcie clock\n");

		goto err_hclk_pcie;

	}



	err = clk_prepare_enable(rockchip->clk_pcie_pm);

	if (err) {

		dev_err(dev, "unable to enable clk_pcie_pm clock\n");

		goto err_clk_pcie_pm;

	}

	err = clk_bulk_prepare_enable(rockchip->num_clks, rockchip->clks);

	if (err)

		return dev_err_probe(dev, err, "failed to enable clocks\n");



	return 0;



err_clk_pcie_pm:

	clk_disable_unprepare(rockchip->hclk_pcie);

err_hclk_pcie:

	clk_disable_unprepare(rockchip->aclk_perf_pcie);

err_aclk_perf_pcie:

	clk_disable_unprepare(rockchip->aclk_pcie);

	return err;

}

EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);



void rockchip_pcie_disable_clocks(void *data)

void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip)

{

	struct rockchip_pcie *rockchip = data;



	clk_disable_unprepare(rockchip->clk_pcie_pm);

	clk_disable_unprepare(rockchip->hclk_pcie);

	clk_disable_unprepare(rockchip->aclk_perf_pcie);

	clk_disable_unprepare(rockchip->aclk_pcie);

	clk_bulk_disable_unprepare(rockchip->num_clks, rockchip->clks);

}

EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);

drivers/pci/controller/pcie-rockchip.h

+23 −12
Original line number Diff line number Diff line
@@ -11,9 +11,11 @@ 
#ifndef _PCIE_ROCKCHIP_H

#define _PCIE_ROCKCHIP_H



#include <linux/clk.h>

#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/pci-ecam.h>

#include <linux/reset.h>



/*

 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
@@ -309,22 +311,31 @@ 
		(((c) << ((b) * 8 + 5)) & \

		 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))



#define ROCKCHIP_NUM_PM_RSTS   ARRAY_SIZE(rockchip_pci_pm_rsts)

#define ROCKCHIP_NUM_CORE_RSTS ARRAY_SIZE(rockchip_pci_core_rsts)



static const char * const rockchip_pci_pm_rsts[] = {

	"pm",

	"pclk",

	"aclk",

};



static const char * const rockchip_pci_core_rsts[] = {

	"mgmt-sticky",

	"core",

	"mgmt",

	"pipe",

};



struct rockchip_pcie {

	void	__iomem *reg_base;		/* DT axi-base */

	void	__iomem *apb_base;		/* DT apb-base */

	bool    legacy_phy;

	struct  phy *phys[MAX_LANE_NUM];

	struct	reset_control *core_rst;

	struct	reset_control *mgmt_rst;

	struct	reset_control *mgmt_sticky_rst;

	struct	reset_control *pipe_rst;

	struct	reset_control *pm_rst;

	struct	reset_control *aclk_rst;

	struct	reset_control *pclk_rst;

	struct	clk *aclk_pcie;

	struct	clk *aclk_perf_pcie;

	struct	clk *hclk_pcie;

	struct	clk *clk_pcie_pm;

	struct  reset_control_bulk_data pm_rsts[ROCKCHIP_NUM_PM_RSTS];

	struct  reset_control_bulk_data core_rsts[ROCKCHIP_NUM_CORE_RSTS];

	struct  clk_bulk_data *clks;

	int	num_clks;

	struct	regulator *vpcie12v; /* 12V power supply */

	struct	regulator *vpcie3v3; /* 3.3V power supply */

	struct	regulator *vpcie1v8; /* 1.8V power supply */
@@ -358,7 +369,7 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip); 
int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip);

void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip);

int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip);

void rockchip_pcie_disable_clocks(void *data);

void rockchip_pcie_disable_clocks(struct rockchip_pcie *rockchip);

void rockchip_pcie_cfg_configuration_accesses(

		struct rockchip_pcie *rockchip, u32 type);