Loading arch/arm/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -78,7 +78,7 @@ menu "System Type" choice prompt "ARM system type" default ARCH_RPC default ARCH_VERSATILE config ARCH_CLPS7500 bool "Cirrus-CL-PS7500FE" Loading arch/arm/mach-ixp4xx/nas100d-power.c +3 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,9 @@ static int __init nas100d_power_init(void) static void __exit nas100d_power_exit(void) { if (!(machine_is_nas100d())) return; free_irq(NAS100D_RB_IRQ, NULL); } Loading arch/arm/mm/tlb-v6.S +1 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier mov pc, lr .section ".text.init", #alloc, #execinstr Loading include/asm-arm/tlbflush.h +6 −0 Original line number Diff line number Diff line Loading @@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); /* The ARM ARM states that the completion of a TLB maintenance * operation is only guaranteed by a DSB instruction */ if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); } /* Loading Loading
arch/arm/Kconfig +1 −1 Original line number Diff line number Diff line Loading @@ -78,7 +78,7 @@ menu "System Type" choice prompt "ARM system type" default ARCH_RPC default ARCH_VERSATILE config ARCH_CLPS7500 bool "Cirrus-CL-PS7500FE" Loading
arch/arm/mach-ixp4xx/nas100d-power.c +3 −0 Original line number Diff line number Diff line Loading @@ -56,6 +56,9 @@ static int __init nas100d_power_init(void) static void __exit nas100d_power_exit(void) { if (!(machine_is_nas100d())) return; free_irq(NAS100D_RB_IRQ, NULL); } Loading
arch/arm/mm/tlb-v6.S +1 −0 Original line number Diff line number Diff line Loading @@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier mov pc, lr .section ".text.init", #alloc, #execinstr Loading
include/asm-arm/tlbflush.h +6 −0 Original line number Diff line number Diff line Loading @@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr)); if (tlb_flag(TLB_V6_I_PAGE)) asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr)); /* The ARM ARM states that the completion of a TLB maintenance * operation is only guaranteed by a DSB instruction */ if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero)); } /* Loading