Commit d42d8e82 authored by William Zhang's avatar William Zhang Committed by Miquel Raynal
Browse files

ARM: dts: broadcom: bcmbca: Add NAND controller node 



Add support for Broadcom STB NAND controller in BCMBCA ARMv7 chip dts
files.

Signed-off-by: default avatarWilliam Zhang <william.zhang@broadcom.com>
Reviewed-by: default avatarDavid Regan <dregan@broadcom.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Acked-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/linux-mtd/20240223034758.13753-8-william.zhang@broadcom.com
parent 280962d4

arch/arm/boot/dts/broadcom/bcm47622.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -138,6 +138,20 @@ hsspi: spi@1000 { 
			status = "disabled";

		};



		nand_controller: nand-controller@1800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";

			reg = <0x1800 0x600>, <0x2000 0x10>;

			reg-names = "nand", "nand-int-base";

			status = "disabled";



			nandcs: nand@0 {

				compatible = "brcm,nandcs";

				reg = <0>;

			};

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

arch/arm/boot/dts/broadcom/bcm63138.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -229,7 +229,12 @@ nand_controller: nand-controller@2000 { 
			reg-names = "nand", "nand-int-base";

			status = "disabled";

			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "nand";

			interrupt-names = "nand_ctlrdy";



			nandcs: nand@0 {

				compatible = "brcm,nandcs";

				reg = <0>;

			};

		};



		serial@4400 {

arch/arm/boot/dts/broadcom/bcm63148.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -119,5 +119,19 @@ hsspi: spi@1000 { 
			num-cs = <8>;

			status = "disabled";

		};



		nand_controller: nand-controller@2000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";

			reg = <0x2000 0x600>, <0xf0 0x10>;

			reg-names = "nand", "nand-int-base";

			status = "disabled";



			nandcs: nand@0 {

				compatible = "brcm,nandcs";

				reg = <0>;

			};

		};

	};

};

arch/arm/boot/dts/broadcom/bcm63178.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -129,6 +129,20 @@ hsspi: spi@1000 { 
			status = "disabled";

		};



		nand_controller: nand-controller@1800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";

			reg = <0x1800 0x600>, <0x2000 0x10>;

			reg-names = "nand", "nand-int-base";

			status = "disabled";



			nandcs: nand@0 {

				compatible = "brcm,nandcs";

				reg = <0>;

			};

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;

arch/arm/boot/dts/broadcom/bcm6756.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -139,6 +139,20 @@ hsspi: spi@1000 { 
			status = "disabled";

		};



		nand_controller: nand-controller@1800 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";

			reg = <0x1800 0x600>, <0x2000 0x10>;

			reg-names = "nand", "nand-int-base";

			status = "disabled";



			nandcs: nand@0 {

				compatible = "brcm,nandcs";

				reg = <0>;

			};

		};



		uart0: serial@12000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x12000 0x1000>;