Commit d457918c authored by Ankit Nautiyal's avatar Ankit Nautiyal
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drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine



Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead.
While at it, use REG_BIT macro for the bits.

Signed-off-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-4-ankit.k.nautiyal@intel.com
parent a64d9afc
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+4 −4
Original line number Diff line number Diff line
@@ -770,9 +770,9 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)

	intel_dsc_pps_configure(crtc_state);

	dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE;
	dss_ctl2_val |= VDSC0_ENABLE;
	if (vdsc_instances_per_pipe > 1) {
		dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE;
		dss_ctl2_val |= VDSC1_ENABLE;
		dss_ctl1_val |= JOINER_ENABLE;
	}
	if (crtc_state->joiner_pipes) {
@@ -972,11 +972,11 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
	dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder));
	dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder));

	crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE;
	crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
	if (!crtc_state->dsc.compression_enable)
		goto out;

	if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE)
	if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
		crtc_state->dsc.num_streams = 2;
	else
		crtc_state->dsc.num_streams = 1;
+2 −2
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@
#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5a0

#define DSS_CTL2				_MMIO(0x67404)
#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
#define  VDSC0_ENABLE				REG_BIT(31)
#define  VDSC1_ENABLE				REG_BIT(15)
#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)