Commit d47cc89d authored by Tomasz Lis's avatar Tomasz Lis Committed by Michał Winiarski
Browse files

drm/xe/sa: Avoid caching GGTT address within the manager 



Non-virtualized resources require fixups after SRIOV VF migration.
Caching GGTT references rather than re-computing them from the
underlying Buffer Object is something we want to avoid, as such
code would require additional fixup step and additional locking
around all the places where the address is accessed.

This change removes the cached GPU address from the Sub-Allocation
Manager, and introduces a function which recomputes and returns
the address instead.

v2: renamed xe_sa_manager_gpu_addr(), added kerneldoc

Signed-off-by: default avatarTomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://lore.kernel.org/r/20250802031045.1127138-2-tomasz.lis@intel.com


Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
parent 0521a868

drivers/gpu/drm/xe/xe_gt_debugfs.c

+3 −2
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#include "xe_pm.h"

#include "xe_reg_sr.h"

#include "xe_reg_whitelist.h"

#include "xe_sa.h"

#include "xe_sriov.h"

#include "xe_tuning.h"

#include "xe_uc_debugfs.h"
@@ -128,7 +129,7 @@ static int sa_info(struct xe_gt *gt, struct drm_printer *p) 


	xe_pm_runtime_get(gt_to_xe(gt));

	drm_suballoc_dump_debug_info(&tile->mem.kernel_bb_pool->base, p,

				     tile->mem.kernel_bb_pool->gpu_addr);

				     xe_sa_manager_gpu_addr(tile->mem.kernel_bb_pool));

	xe_pm_runtime_put(gt_to_xe(gt));



	return 0;
@@ -152,7 +153,7 @@ static int sa_info_vf_ccs(struct xe_gt *gt, struct drm_printer *p) 


		drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");

		drm_printf(p, "-------------------------\n");

		drm_suballoc_dump_debug_info(&bb_pool->base, p, bb_pool->gpu_addr);

		drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool));

		drm_puts(p, "\n");

	}

drivers/gpu/drm/xe/xe_guc_buf.c

+1 −1
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ u64 xe_guc_cache_gpu_addr_from_ptr(struct xe_guc_buf_cache *cache, const void *p 
	if (offset < 0 || offset + size > cache->sam->base.size)

		return 0;



	return cache->sam->gpu_addr + offset;

	return xe_sa_manager_gpu_addr(cache->sam) + offset;

}



#if IS_BUILTIN(CONFIG_DRM_XE_KUNIT_TEST)

drivers/gpu/drm/xe/xe_sa.c

+0 −1
Original line number Diff line number Diff line
@@ -69,7 +69,6 @@ struct xe_sa_manager *__xe_sa_bo_manager_init(struct xe_tile *tile, u32 size, u3 
	}

	sa_manager->bo = bo;

	sa_manager->is_iomem = bo->vmap.is_iomem;

	sa_manager->gpu_addr = xe_bo_ggtt_addr(bo);



	if (bo->vmap.is_iomem) {

		sa_manager->cpu_ptr = kvzalloc(managed_size, GFP_KERNEL);

drivers/gpu/drm/xe/xe_sa.h

+14 −1
Original line number Diff line number Diff line
@@ -7,6 +7,8 @@ 


#include <linux/sizes.h>

#include <linux/types.h>



#include "xe_bo.h"

#include "xe_sa_types.h"



struct dma_fence;
@@ -43,9 +45,20 @@ to_xe_sa_manager(struct drm_suballoc_manager *mng) 
	return container_of(mng, struct xe_sa_manager, base);

}



/**

 * xe_sa_manager_gpu_addr - Retrieve GPU address of a back storage BO

 * within suballocator.

 * @sa_manager: the &xe_sa_manager struct instance

 * Return: GGTT address of the back storage BO.

 */

static inline u64 xe_sa_manager_gpu_addr(struct xe_sa_manager *sa_manager)

{

	return xe_bo_ggtt_addr(sa_manager->bo);

}



static inline u64 xe_sa_bo_gpu_addr(struct drm_suballoc *sa)

{

	return to_xe_sa_manager(sa->manager)->gpu_addr +

	return xe_sa_manager_gpu_addr(to_xe_sa_manager(sa->manager)) +

		drm_suballoc_soffset(sa);

}

drivers/gpu/drm/xe/xe_sa_types.h

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ struct xe_bo; 
struct xe_sa_manager {

	struct drm_suballoc_manager base;

	struct xe_bo *bo;

	u64 gpu_addr;

	void *cpu_ptr;

	bool is_iomem;

};