Unverified Commit d4c8d79f authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
Browse files

riscv: cpufeature: Extract common elements from extension checking 



The __riscv_has_extension_likely() and __riscv_has_extension_unlikely()
functions from the vendor_extensions.h can be used to simplify the
standard extension checking code as well. Migrate those functions to
cpufeature.h and reorganize the code in the file to use the functions.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Link: https://lore.kernel.org/r/20240719-support_vendor_extensions-v3-4-0af7587bbec0@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 0f242541

arch/riscv/include/asm/cpufeature.h

+44 −34
Original line number Diff line number Diff line
@@ -104,59 +104,66 @@ extern bool riscv_isa_fallback; 


unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



#define STANDARD_EXT		0



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



static __always_inline bool

riscv_has_extension_likely(const unsigned long ext)

static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor,

							 const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm goto(

		ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)

	asm goto(ALTERNATIVE("j	%l[l_no]", "nop", %[vendor], %[ext], 1)

	:

		: [ext] "i" (ext)

	: [vendor] "i" (vendor), [ext] "i" (ext)

	:

	: l_no);

	} else {

		if (!__riscv_isa_extension_available(NULL, ext))

			goto l_no;

	}



	return true;

l_no:

	return false;

}



static __always_inline bool

riscv_has_extension_unlikely(const unsigned long ext)

static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor,

							   const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm goto(

		ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)

	asm goto(ALTERNATIVE("nop", "j	%l[l_yes]", %[vendor], %[ext], 1)

	:

		: [ext] "i" (ext)

	: [vendor] "i" (vendor), [ext] "i" (ext)

	:

	: l_yes);

	} else {

		if (__riscv_isa_extension_available(NULL, ext))

			goto l_yes;

	}



	return false;

l_yes:

	return true;

}



static __always_inline bool riscv_has_extension_unlikely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))

		return __riscv_has_extension_unlikely(STANDARD_EXT, ext);



	return __riscv_isa_extension_available(NULL, ext);

}



static __always_inline bool riscv_has_extension_likely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE))

		return __riscv_has_extension_likely(STANDARD_EXT, ext);



	return __riscv_isa_extension_available(NULL, ext);

}



static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))

	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) &&

	    __riscv_has_extension_likely(STANDARD_EXT, ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
@@ -164,7 +171,10 @@ static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsign 


static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)

{

	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))

	compiletime_assert(ext < RISCV_ISA_EXT_MAX, "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) &&

	    __riscv_has_extension_unlikely(STANDARD_EXT, ext))

		return true;



	return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);

arch/riscv/include/asm/vendor_extensions.h

+0 −28
Original line number Diff line number Diff line
@@ -48,34 +48,6 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig 
	__riscv_isa_vendor_extension_available(VENDOR_EXT_ALL_CPUS, vendor, \

					       RISCV_ISA_VENDOR_EXT_##ext)



static __always_inline bool __riscv_has_extension_likely(const unsigned long vendor,

							 const unsigned long ext)

{

	asm goto(ALTERNATIVE("j	%l[l_no]", "nop", %[vendor], %[ext], 1)

	:

	: [vendor] "i" (vendor), [ext] "i" (ext)

	:

	: l_no);



	return true;

l_no:

	return false;

}



static __always_inline bool __riscv_has_extension_unlikely(const unsigned long vendor,

							   const unsigned long ext)

{

	asm goto(ALTERNATIVE("nop", "j	%l[l_yes]", %[vendor], %[ext], 1)

	:

	: [vendor] "i" (vendor), [ext] "i" (ext)

	:

	: l_yes);



	return false;

l_yes:

	return true;

}



static __always_inline bool riscv_has_vendor_extension_likely(const unsigned long vendor,

							      const unsigned long ext)

{