Commit d4ca1a8b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Andi Shyti
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drm/i915: Reoder CHV EU/slice fuse bits 



We customarily define the bits of a register in big endian
order. Reorder the CHV fuse bits to match.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-9-ville.syrjala@linux.intel.com
parent dcf99692

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+8 −8
Original line number Diff line number Diff line
@@ -937,10 +937,10 @@ 
#define CHV_POWER_SS0_SIG1			_MMIO(0xa720)

#define CHV_POWER_SS0_SIG2			_MMIO(0xa724)

#define CHV_POWER_SS1_SIG1			_MMIO(0xa728)

#define   CHV_SS_PG_ENABLE			REG_BIT(1)

#define   CHV_EU08_PG_ENABLE			REG_BIT(9)

#define   CHV_EU19_PG_ENABLE			REG_BIT(17)

#define   CHV_EU210_PG_ENABLE			REG_BIT(25)

#define   CHV_EU19_PG_ENABLE			REG_BIT(17)

#define   CHV_EU08_PG_ENABLE			REG_BIT(9)

#define   CHV_SS_PG_ENABLE			REG_BIT(1)

#define CHV_POWER_SS1_SIG2			_MMIO(0xa72c)

#define   CHV_EU311_PG_ENABLE			REG_BIT(1)
@@ -1440,12 +1440,12 @@ 
#define   XEHP_CCS_MODE_CSLICE(cslice, ccs)	(ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))



#define CHV_FUSE_GT				_MMIO(VLV_GUNIT_BASE + 0x2168)

#define   CHV_FGT_DISABLE_SS0			REG_BIT(10)

#define   CHV_FGT_DISABLE_SS1			REG_BIT(11)

#define   CHV_FGT_EU_DIS_SS0_R0_MASK		REG_GENMASK(19, 16)

#define   CHV_FGT_EU_DIS_SS0_R1_MASK		REG_GENMASK(23, 20)

#define   CHV_FGT_EU_DIS_SS1_R0_MASK		REG_GENMASK(27, 24)

#define   CHV_FGT_EU_DIS_SS1_R1_MASK		REG_GENMASK(31, 28)

#define   CHV_FGT_EU_DIS_SS1_R0_MASK		REG_GENMASK(27, 24)

#define   CHV_FGT_EU_DIS_SS0_R1_MASK		REG_GENMASK(23, 20)

#define   CHV_FGT_EU_DIS_SS0_R0_MASK		REG_GENMASK(19, 16)

#define   CHV_FGT_DISABLE_SS1			REG_BIT(11)

#define   CHV_FGT_DISABLE_SS0			REG_BIT(10)



#define BCS_SWCTRL				_MMIO(0x22200)

#define   BCS_SRC_Y				REG_BIT(0)