Commit d4da3adf authored by Vikram Sharma's avatar Vikram Sharma Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sc7280: Add support for camss 



Add changes to support the camera subsystem on the SC7280.

Signed-off-by: default avatarSuresh Vankadara <quic_svankada@quicinc.com>
Signed-off-by: default avatarTrishansh Bhardwaj <quic_tbhardwa@quicinc.com>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: default avatarVikram Sharma <quic_vikramsa@quicinc.com>
Acked-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20250208225143.2868279-2-quic_vikramsa@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 4f4c905e

arch/arm64/boot/dts/qcom/sc7280.dtsi

+178 −0
Original line number Diff line number Diff line
@@ -4422,6 +4422,184 @@ cci1_i2c1: i2c-bus@1 { 
			};

		};



		camss: isp@acb3000 {

			compatible = "qcom,sc7280-camss";



			reg = <0x0 0x0acb3000 0x0 0x1000>,

			      <0x0 0x0acba000 0x0 0x1000>,

			      <0x0 0x0acc1000 0x0 0x1000>,

			      <0x0 0x0acc8000 0x0 0x1000>,

			      <0x0 0x0accf000 0x0 0x1000>,

			      <0x0 0x0ace0000 0x0 0x2000>,

			      <0x0 0x0ace2000 0x0 0x2000>,

			      <0x0 0x0ace4000 0x0 0x2000>,

			      <0x0 0x0ace6000 0x0 0x2000>,

			      <0x0 0x0ace8000 0x0 0x2000>,

			      <0x0 0x0acaf000 0x0 0x4000>,

			      <0x0 0x0acb6000 0x0 0x4000>,

			      <0x0 0x0acbd000 0x0 0x4000>,

			      <0x0 0x0acc4000 0x0 0x4000>,

			      <0x0 0x0accb000 0x0 0x4000>;

			reg-names = "csid0",

				    "csid1",

				    "csid2",

				    "csid_lite0",

				    "csid_lite1",

				    "csiphy0",

				    "csiphy1",

				    "csiphy2",

				    "csiphy3",

				    "csiphy4",

				    "vfe0",

				    "vfe1",

				    "vfe2",

				    "vfe_lite0",

				    "vfe_lite1";



			clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,

				 <&camcc CAM_CC_CPAS_AHB_CLK>,

				 <&camcc CAM_CC_CSIPHY0_CLK>,

				 <&camcc CAM_CC_CSI0PHYTIMER_CLK>,

				 <&camcc CAM_CC_CSIPHY1_CLK>,

				 <&camcc CAM_CC_CSI1PHYTIMER_CLK>,

				 <&camcc CAM_CC_CSIPHY2_CLK>,

				 <&camcc CAM_CC_CSI2PHYTIMER_CLK>,

				 <&camcc CAM_CC_CSIPHY3_CLK>,

				 <&camcc CAM_CC_CSI3PHYTIMER_CLK>,

				 <&camcc CAM_CC_CSIPHY4_CLK>,

				 <&camcc CAM_CC_CSI4PHYTIMER_CLK>,

				 <&gcc GCC_CAMERA_HF_AXI_CLK>,

				 <&gcc GCC_CAMERA_SF_AXI_CLK>,

				 <&camcc CAM_CC_ICP_AHB_CLK>,

				 <&camcc CAM_CC_IFE_0_CLK>,

				 <&camcc CAM_CC_IFE_0_AXI_CLK>,

				 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,

				 <&camcc CAM_CC_IFE_0_CSID_CLK>,

				 <&camcc CAM_CC_IFE_1_CLK>,

				 <&camcc CAM_CC_IFE_1_AXI_CLK>,

				 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,

				 <&camcc CAM_CC_IFE_1_CSID_CLK>,

				 <&camcc CAM_CC_IFE_2_CLK>,

				 <&camcc CAM_CC_IFE_2_AXI_CLK>,

				 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,

				 <&camcc CAM_CC_IFE_2_CSID_CLK>,

				 <&camcc CAM_CC_IFE_LITE_0_CLK>,

				 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,

				 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,

				 <&camcc CAM_CC_IFE_LITE_1_CLK>,

				 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,

				 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;

			clock-names = "camnoc_axi",

				      "cpas_ahb",

				      "csiphy0",

				      "csiphy0_timer",

				      "csiphy1",

				      "csiphy1_timer",

				      "csiphy2",

				      "csiphy2_timer",

				      "csiphy3",

				      "csiphy3_timer",

				      "csiphy4",

				      "csiphy4_timer",

				      "gcc_axi_hf",

				      "gcc_axi_sf",

				      "icp_ahb",

				      "vfe0",

				      "vfe0_axi",

				      "vfe0_cphy_rx",

				      "vfe0_csid",

				      "vfe1",

				      "vfe1_axi",

				      "vfe1_cphy_rx",

				      "vfe1_csid",

				      "vfe2",

				      "vfe2_axi",

				      "vfe2_cphy_rx",

				      "vfe2_csid",

				      "vfe_lite0",

				      "vfe_lite0_cphy_rx",

				      "vfe_lite0_csid",

				      "vfe_lite1",

				      "vfe_lite1_cphy_rx",

				      "vfe_lite1_csid";



			interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,

				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;

			interrupt-names = "csid0",

					  "csid1",

					  "csid2",

					  "csid_lite0",

					  "csid_lite1",

					  "csiphy0",

					  "csiphy1",

					  "csiphy2",

					  "csiphy3",

					  "csiphy4",

					  "vfe0",

					  "vfe1",

					  "vfe2",

					  "vfe_lite0",

					  "vfe_lite1";



			interconnects = <&gem_noc  MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY

					 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,

					<&mmss_noc MASTER_CAMNOC_HF  QCOM_ICC_TAG_ALWAYS

					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;

			interconnect-names = "ahb",

					     "hf_0";



			iommus = <&apps_smmu 0x800 0x4e0>;



			power-domains = <&camcc CAM_CC_IFE_0_GDSC>,

					<&camcc CAM_CC_IFE_1_GDSC>,

					<&camcc CAM_CC_IFE_2_GDSC>,

					<&camcc CAM_CC_TITAN_TOP_GDSC>;

			power-domain-names = "ife0",

					     "ife1",

					     "ife2",

					     "top";



			status = "disabled";



			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

				};



				port@1 {

					reg = <1>;

				};



				port@2 {

					reg = <2>;

				};



				port@3 {

					reg = <3>;

				};



				port@4 {

					reg = <4>;

				};

			};

		};



		camcc: clock-controller@ad00000 {

			compatible = "qcom,sc7280-camcc";

			reg = <0 0x0ad00000 0 0x10000>;