Commit d4e034b4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "New HW support:
   - Freescale i.MX8ULP edma support in edma driver
   - StarFive JH8100 DMA support in Synopsis axi-dmac driver

  Updates:
   - Tracing support for freescale edma driver, updates to dpaa2 driver
   - Remove unused QCom hidma DT support
   - Support for i2c dma in imx-sdma
   - Maintainers update for idxd and edma drivers"

* tag 'dmaengine-6.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (42 commits)
  MAINTAINERS: Update role for IDXD driver
  dmaengine: fsl-edma: use _Generic to handle difference type
  dmaengine: fsl-edma: add trace event support
  dmaengine: idxd: Avoid unnecessary destruction of file_ida
  dmaengine: xilinx: xdma: fix module autoloading
  dt-bindings: dma: fsl-edma: allow 'power-domains' property
  dt-bindings: dma: fsl-edma: remove 'clocks' from required
  dmaengine: fsl-dpaa2-qdma: Fix kernel-doc check warning
  dmaengine: imx-sdma: Add i2c dma support
  dmaengine: imx-sdma: utilize compiler to calculate ADDRS_ARRAY_SIZE_V<n>
  dt-bindings: fsl-imx-sdma: Add I2C peripheral types ID
  dt-bindings: fsl-dma: fsl-edma: clean up unused "fsl,imx8qm-adma" compatible string
  dmaengine: fsl-edma: clean up unused "fsl,imx8qm-adma" compatible string
  dt-bindings: dma: Drop unused QCom hidma binding
  dmaengine: qcom: Drop hidma DT support
  dmaengine: pl08x: Use kcalloc() instead of kzalloc()
  dmaengine: fsl-dpaa2-qdma: Update DPDMAI interfaces to version 3
  dmaengine: fsl-edma: fix miss mutex unlock at an error return path
  dmaengine: pch_dma: remove unused function chan2parent
  dmaengine: fsl-dpaa2-qdma: Add dpdmai_cmd_open
  ...
parents 34dcc466 28059ddb

Documentation/devicetree/bindings/dma/fsl,edma.yaml

+96 −43
Original line number Diff line number Diff line
@@ -21,8 +21,8 @@ properties: 
      - enum:

          - fsl,vf610-edma

          - fsl,imx7ulp-edma

          - fsl,imx8qm-adma

          - fsl,imx8qm-edma

          - fsl,imx8ulp-edma

          - fsl,imx93-edma3

          - fsl,imx93-edma4

          - fsl,imx95-edma5
@@ -43,6 +43,17 @@ properties: 
    maxItems: 64



  "#dma-cells":

    description: |

      Specifies the number of cells needed to encode an DMA channel.



      Encode for cells number 2:

        cell 0: index of dma channel mux instance.

        cell 1: peripheral dma request id.



      Encode for cells number 3:

        cell 0: peripheral dma request id.

        cell 1: dma channel priority.

        cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h

    enum:

      - 2

      - 3
@@ -53,11 +64,18 @@ properties: 


  clocks:

    minItems: 1

    maxItems: 2

    maxItems: 33



  clock-names:

    minItems: 1

    maxItems: 2

    maxItems: 33



  power-domains:

    description:

      The number of power domains matches the number of channels, arranged

      in ascending order according to their associated DMA channels.

    minItems: 1

    maxItems: 64



  big-endian:

    description: |
@@ -70,7 +88,6 @@ required: 
  - compatible

  - reg

  - interrupts

  - clocks

  - dma-channels



allOf:
@@ -80,7 +97,6 @@ allOf: 
        compatible:

          contains:

            enum:

              - fsl,imx8qm-adma

              - fsl,imx8qm-edma

              - fsl,imx93-edma3

              - fsl,imx93-edma4
@@ -108,6 +124,7 @@ allOf: 
      properties:

        clocks:

          minItems: 2

          maxItems: 2

        clock-names:

          items:

            - const: dmamux0
@@ -136,6 +153,7 @@ allOf: 
      properties:

        clock:

          minItems: 2

          maxItems: 2

        clock-names:

          items:

            - const: dma
@@ -151,6 +169,58 @@ allOf: 
        dma-channels:

          const: 32



  - if:

      properties:

        compatible:

          contains:

            const: fsl,imx8ulp-edma

    then:

      properties:

        clocks:

          minItems: 33

        clock-names:

          minItems: 33

          items:

            oneOf:

              - const: dma

              - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"



        interrupt-names: false

        interrupts:

          minItems: 32

        "#dma-cells":

          const: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,vf610-edma

              - fsl,imx7ulp-edma

              - fsl,imx93-edma3

              - fsl,imx93-edma4

              - fsl,imx95-edma5

              - fsl,imx8ulp-edma

              - fsl,ls1028a-edma

    then:

      required:

        - clocks



  - if:

      properties:

        compatible:

          contains:

            enum:

              - fsl,imx8qm-adma

              - fsl,imx8qm-edma

    then:

      required:

        - power-domains

    else:

      properties:

        power-domains: false



unevaluatedProperties: false



examples:
@@ -206,44 +276,27 @@ examples: 


  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/imx93-clock.h>

    #include <dt-bindings/firmware/imx/rsrc.h>



    dma-controller@44000000 {

      compatible = "fsl,imx93-edma3";

      reg = <0x44000000 0x200000>;

    dma-controller@5a9f0000 {

      compatible = "fsl,imx8qm-edma";

      reg = <0x5a9f0000 0x90000>;

      #dma-cells = <3>;

      dma-channels = <31>;

      interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&clk IMX93_CLK_EDMA1_GATE>;

        clock-names = "dma";

      dma-channels = <8>;

      interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,

                   <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;

      power-domains = <&pd IMX_SC_R_DMA_3_CH0>,

                      <&pd IMX_SC_R_DMA_3_CH1>,

                      <&pd IMX_SC_R_DMA_3_CH2>,

                      <&pd IMX_SC_R_DMA_3_CH3>,

                      <&pd IMX_SC_R_DMA_3_CH4>,

                      <&pd IMX_SC_R_DMA_3_CH5>,

                      <&pd IMX_SC_R_DMA_3_CH6>,

                      <&pd IMX_SC_R_DMA_3_CH7>;

    };

Documentation/devicetree/bindings/dma/fsl,imx-sdma.yaml

+1 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ properties: 
          - SAI: 24

          - Multi SAI: 25

          - HDMI Audio: 26

          - I2C: 27



       The third cell: transfer priority ID

         enum:

Documentation/devicetree/bindings/dma/qcom_hidma_mgmt.txt

deleted100644 → 0
+0 −95
Original line number Diff line number Diff line 
Qualcomm Technologies HIDMA Management interface



Qualcomm Technologies HIDMA is a high speed DMA device. It only supports

memcpy and memset capabilities. It has been designed for virtualized

environments.



Each HIDMA HW instance consists of multiple DMA channels. These channels

share the same bandwidth. The bandwidth utilization can be partitioned

among channels based on the priority and weight assignments.



There are only two priority levels and 15 weigh assignments possible.



Other parameters here determine how much of the system bus this HIDMA

instance can use like maximum read/write request and number of bytes to

read/write in a single burst.



Main node required properties:

- compatible: "qcom,hidma-mgmt-1.0";

- reg: Address range for DMA device

- dma-channels: Number of channels supported by this DMA controller.

- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can

  occupy the bus for in a single transaction. A memcpy requested is

  fragmented to multiples of this amount. This parameter is used while

  writing into destination memory. Setting this value incorrectly can

  starve other peripherals in the system.

- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can

  occupy the bus for in a single transaction. A memcpy request is

  fragmented to multiples of this amount. This parameter is used while

  reading the source memory. Setting this value incorrectly can starve

  other peripherals in the system.

- max-write-transactions: This value is how many times a write burst is

  applied back to back while writing to the destination before yielding

  the bus.

- max-read-transactions: This value is how many times a read burst is

  applied back to back while reading the source before yielding the bus.

- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.

  Once a reset is applied to the HW, HW starts a timer for reset operation

  to confirm. If reset is not completed within this time, HW reports reset

  failure.



Sub-nodes:



HIDMA has one or more DMA channels that are used to move data from one

memory location to another.



When the OS is not in control of the management interface (i.e. it's a guest),

the channel nodes appear on their own, not under a management node.



Required properties:

- compatible: must contain "qcom,hidma-1.0" for initial HW or

  "qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.

- reg: Addresses for the transfer and event channel

- interrupts: Should contain the event interrupt

- desc-count: Number of asynchronous requests this channel can handle

- iommus: required a iommu node



Optional properties for MSI:

- msi-parent : See the generic MSI binding described in

 devicetree/bindings/interrupt-controller/msi.txt for a description of the

 msi-parent property.



Example:



Hypervisor OS configuration:



	hidma-mgmt@f9984000 = {

		compatible = "qcom,hidma-mgmt-1.0";

		reg = <0xf9984000 0x15000>;

		dma-channels = <6>;

		max-write-burst-bytes = <1024>;

		max-read-burst-bytes = <1024>;

		max-write-transactions = <31>;

		max-read-transactions = <31>;

		channel-reset-timeout-cycles = <0x500>;



		hidma_24: dma-controller@5c050000 {

			compatible = "qcom,hidma-1.0";

			reg = <0 0x5c050000 0x0 0x1000>,

			      <0 0x5c0b0000 0x0 0x1000>;

			interrupts = <0 389 0>;

			desc-count = <10>;

			iommus = <&system_mmu>;

		};

	};



Guest OS configuration:



	hidma_24: dma-controller@5c050000 {

		compatible = "qcom,hidma-1.0";

		reg = <0 0x5c050000 0x0 0x1000>,

		      <0 0x5c0b0000 0x0 0x1000>;

		interrupts = <0 389 0>;

		desc-count = <10>;

		iommus = <&system_mmu>;

	};

Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml

+21 −21
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ properties: 
  data-width:

    $ref: /schemas/types.yaml#/definitions/uint32-array

    description: Data bus width per each DMA master in bytes.

    items:

    minItems: 1

    maxItems: 4

    items:

      enum: [4, 8, 16, 32]
@@ -106,7 +106,7 @@ properties: 
      deprecated. It' usage is discouraged in favor of data-width one. Moreover

      the property incorrectly permits to define data-bus width of 8 and 16

      bits, which is impossible in accordance with DW DMAC IP-core data book.

    items:

    minItems: 1

    maxItems: 4

    items:

      enum:
@@ -123,7 +123,7 @@ properties: 
    description: |

      LLP-based multi-block transfer supported by hardware per

      each DMA channel.

    items:

    minItems: 1

    maxItems: 8

    items:

      enum: [0, 1]
@@ -138,7 +138,7 @@ properties: 
      will be from 1 to max-burst-len words. It's an array property with one

      cell per channel in the units determined by the value set in the

      CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).

    items:

    minItems: 1

    maxItems: 8

    items:

      enum: [4, 8, 16, 32, 64, 128, 256]

Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

+1 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ properties: 
      - snps,axi-dma-1.01a

      - intel,kmb-axi-dma

      - starfive,jh7110-axi-dma

      - starfive,jh8100-axi-dma



  reg:

    minItems: 1