Commit d50bf3f0 authored by Harish Kasiviswanathan's avatar Harish Kasiviswanathan Committed by Alex Deucher
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drm/amdkfd: hard-code MALL cacheline size for gfx11, gfx12 



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Signed-off-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: default avatarDavid Belanger <david.belanger@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 321048c4

drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+1 −1
Original line number Diff line number Diff line
@@ -1504,7 +1504,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, 
					CRAT_CACHE_FLAGS_DATA_CACHE |

					CRAT_CACHE_FLAGS_SIMD_CACHE);

		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;

		pcache_info[i].cache_line_size = 0;

		pcache_info[i].cache_line_size = 64;

		i++;

	}

	return i;