Commit d525b0af authored by Rob Clark's avatar Rob Clark Committed by Will Deacon
Browse files

iommu/arm-smmu: Pretty-print context fault related regs 



Parse out the bitfields for easier-to-read fault messages.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarPranjal Shrivastava <praan@google.com>
Link: https://lore.kernel.org/r/20240701162025.375134-4-robdclark@gmail.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 55089781

drivers/iommu/arm/arm-smmu/arm-smmu-qcom-debug.c

+16 −36
Original line number Diff line number Diff line
@@ -383,64 +383,44 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) 
	struct arm_smmu_domain *smmu_domain = dev;

	struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	u32 fsr, fsynr, cbfrsynra, resume = 0;

	struct arm_smmu_context_fault_info cfi;

	u32 resume = 0;

	int idx = smmu_domain->cfg.cbndx;

	phys_addr_t phys_soft;

	unsigned long iova;

	int ret, tmp;



	static DEFINE_RATELIMIT_STATE(_rs,

				      DEFAULT_RATELIMIT_INTERVAL,

				      DEFAULT_RATELIMIT_BURST);



	fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);

	if (!(fsr & ARM_SMMU_CB_FSR_FAULT))

		return IRQ_NONE;

	arm_smmu_read_context_fault_info(smmu, idx, &cfi);



	fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);

	iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);

	cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));

	if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))

		return IRQ_NONE;



	if (list_empty(&tbu_list)) {

		ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,

					 fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);

		ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,

					 cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);



		if (ret == -ENOSYS)

			dev_err_ratelimited(smmu->dev,

					    "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",

					    fsr, iova, fsynr, cbfrsynra, idx);

			arm_smmu_print_context_fault_info(smmu, idx, &cfi);



		arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);

		arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);

		return IRQ_HANDLED;

	}



	phys_soft = ops->iova_to_phys(ops, iova);

	phys_soft = ops->iova_to_phys(ops, cfi.iova);



	tmp = report_iommu_fault(&smmu_domain->domain, NULL, iova,

				 fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);

	tmp = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,

				 cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);

	if (!tmp || tmp == -EBUSY) {

		ret = IRQ_HANDLED;

		resume = ARM_SMMU_RESUME_TERMINATE;

	} else {

		phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, iova, fsr);

		phys_addr_t phys_atos = qcom_smmu_verify_fault(smmu_domain, cfi.iova, cfi.fsr);



		if (__ratelimit(&_rs)) {

			dev_err(smmu->dev,

				"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",

				fsr, iova, fsynr, cbfrsynra, idx);

			dev_err(smmu->dev,

				"FSR    = %08x [%s%s%s%s%s%s%s%s%s], SID=0x%x\n",

				fsr,

				(fsr & 0x02) ? "TF " : "",

				(fsr & 0x04) ? "AFF " : "",

				(fsr & 0x08) ? "PF " : "",

				(fsr & 0x10) ? "EF " : "",

				(fsr & 0x20) ? "TLBMCF " : "",

				(fsr & 0x40) ? "TLBLKF " : "",

				(fsr & 0x80) ? "MHF " : "",

				(fsr & 0x40000000) ? "SS " : "",

				(fsr & 0x80000000) ? "MULTI " : "",

				cbfrsynra);

			arm_smmu_print_context_fault_info(smmu, idx, &cfi);



			dev_err(smmu->dev,

				"soft iova-to-phys=%pa\n", &phys_soft);
@@ -474,10 +454,10 @@ irqreturn_t qcom_smmu_context_fault(int irq, void *dev) 
	 */

	if (tmp != -EBUSY) {

		/* Clear the faulting FSR */

		arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);

		arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);



		/* Retry or terminate any stalled transactions */

		if (fsr & ARM_SMMU_CB_FSR_SS)

		if (cfi.fsr & ARM_SMMU_CB_FSR_SS)

			arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_RESUME, resume);

	}

drivers/iommu/arm/arm-smmu/arm-smmu.c

+55 −15
Original line number Diff line number Diff line
@@ -405,32 +405,72 @@ static const struct iommu_flush_ops arm_smmu_s2_tlb_ops_v1 = { 
	.tlb_add_page	= arm_smmu_tlb_add_page_s2_v1,

};





void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,

				      struct arm_smmu_context_fault_info *cfi)

{

	cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);

	cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);

	cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);

	cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));

}



void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,

				       const struct arm_smmu_context_fault_info *cfi)

{

	dev_dbg(smmu->dev,

		"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",

		cfi->fsr, cfi->iova, cfi->fsynr, cfi->cbfrsynra, idx);



	dev_err(smmu->dev, "FSR    = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n",

		cfi->fsr,

		(cfi->fsr & ARM_SMMU_CB_FSR_MULTI)  ? "MULTI " : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_SS)     ? "SS " : "",

		(u32)FIELD_GET(ARM_SMMU_CB_FSR_FORMAT, cfi->fsr),

		(cfi->fsr & ARM_SMMU_CB_FSR_UUT)    ? " UUT" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_ASF)    ? " ASF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_TLBLKF) ? " TLBLKF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_TLBMCF) ? " TLBMCF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_EF)     ? " EF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_PF)     ? " PF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_AFF)    ? " AFF" : "",

		(cfi->fsr & ARM_SMMU_CB_FSR_TF)     ? " TF" : "",

		cfi->cbfrsynra);



	dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n",

		cfi->fsynr,

		(u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_S1CBNDX, cfi->fsynr),

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_AFR) ? " AFR" : "",

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_PTWF) ? " PTWF" : "",

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_NSATTR) ? " NSATTR" : "",

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_IND) ? " IND" : "",

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_PNU) ? " PNU" : "",

		(cfi->fsynr & ARM_SMMU_CB_FSYNR0_WNR) ? " WNR" : "",

		(u32)FIELD_GET(ARM_SMMU_CB_FSYNR0_PLVL, cfi->fsynr));

}



static irqreturn_t arm_smmu_context_fault(int irq, void *dev)

{

	u32 fsr, fsynr, cbfrsynra;

	unsigned long iova;

	struct arm_smmu_context_fault_info cfi;

	struct arm_smmu_domain *smmu_domain = dev;

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,

				      DEFAULT_RATELIMIT_BURST);

	int idx = smmu_domain->cfg.cbndx;

	int ret;



	fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);

	if (!(fsr & ARM_SMMU_CB_FSR_FAULT))

		return IRQ_NONE;

	arm_smmu_read_context_fault_info(smmu, idx, &cfi);



	fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0);

	iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);

	cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));

	if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT))

		return IRQ_NONE;



	ret = report_iommu_fault(&smmu_domain->domain, NULL, iova,

		fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);

	ret = report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova,

		cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);



	if (ret == -ENOSYS)

		dev_err_ratelimited(smmu->dev,

		"Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",

			    fsr, iova, fsynr, cbfrsynra, idx);

	if (ret == -ENOSYS && __ratelimit(&rs))

		arm_smmu_print_context_fault_info(smmu, idx, &cfi);



	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);

	arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr);

	return IRQ_HANDLED;

}

drivers/iommu/arm/arm-smmu/arm-smmu.h

+21 −0
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ enum arm_smmu_cbar_type { 
#define ARM_SMMU_CB_FSR			0x58

#define ARM_SMMU_CB_FSR_MULTI		BIT(31)

#define ARM_SMMU_CB_FSR_SS		BIT(30)

#define ARM_SMMU_CB_FSR_FORMAT		GENMASK(10, 9)

#define ARM_SMMU_CB_FSR_UUT		BIT(8)

#define ARM_SMMU_CB_FSR_ASF		BIT(7)

#define ARM_SMMU_CB_FSR_TLBLKF		BIT(6)
@@ -223,7 +224,14 @@ enum arm_smmu_cbar_type { 
#define ARM_SMMU_CB_FAR			0x60



#define ARM_SMMU_CB_FSYNR0		0x68

#define ARM_SMMU_CB_FSYNR0_PLVL		GENMASK(1, 0)

#define ARM_SMMU_CB_FSYNR0_WNR		BIT(4)

#define ARM_SMMU_CB_FSYNR0_PNU		BIT(5)

#define ARM_SMMU_CB_FSYNR0_IND		BIT(6)

#define ARM_SMMU_CB_FSYNR0_NSATTR	BIT(8)

#define ARM_SMMU_CB_FSYNR0_PTWF		BIT(10)

#define ARM_SMMU_CB_FSYNR0_AFR		BIT(11)

#define ARM_SMMU_CB_FSYNR0_S1CBNDX	GENMASK(23, 16)



#define ARM_SMMU_CB_FSYNR1		0x6c
@@ -533,4 +541,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); 
void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);

int arm_mmu500_reset(struct arm_smmu_device *smmu);



struct arm_smmu_context_fault_info {

	unsigned long iova;

	u32 fsr;

	u32 fsynr;

	u32 cbfrsynra;

};



void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx,

				      struct arm_smmu_context_fault_info *cfi);



void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx,

				       const struct arm_smmu_context_fault_info *cfi);



#endif /* _ARM_SMMU_H */