Commit d58a73c9 authored by Conor Dooley's avatar Conor Dooley
Browse files

dt-bindings: cache: add specific RZ/Five compatible to ax45mp 



When the binding was originally written, it was assumed that all
ax45mp-caches had the same properties etc. This has turned out to be
incorrect, as the QiLai SoC has a different number of cache-sets.

Add a specific compatible for the RZ/Five for property enforcement and
in case there turns out to be additional differences between these
implementations of the cache controller.

Acked-by: default avatarBen Zong-You Xie <ben717@andestech.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 82e8c693

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

+3 −1
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ select: 
properties:

  compatible:

    items:

      - const: renesas,r9a07g043f-ax45mp-cache

      - const: andestech,ax45mp-cache

      - const: cache
@@ -70,7 +71,8 @@ examples: 
    #include <dt-bindings/interrupt-controller/irq.h>



    cache-controller@13400000 {

        compatible = "andestech,ax45mp-cache", "cache";

        compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",

                     "cache";

        reg = <0x13400000 0x100000>;

        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;

        cache-line-size = <64>;